Paper | Title | Page |
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TUPMA03 | Creation of High-charge Bunch Trains from the APS Injector for Swap-out Injection | 595 |
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Funding: Work supported by the U.S. Department of Energy, Office of Science, under Contract No. DE-AC02-06CH11357. A multi-bend-achromat (MBA) extreme low-emittance lattice has been proposed for the future APS Upgrade. Due to its small dynamic aperture, the traditional injection scheme must be replaced with bunch train swap-out scheme. Several options were considered for the creation of a high-charge bunch train from the injector, and we selected an option that builds the bunch train in the particle accumulator ring (PAR). This option enables both single-bunch mode, which is necessary to support current APS operation, and bunch-train mode. This report provides a description of the injection process, simulation results, and specifications of injector timing, kicker, and rf subsystems. |
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THPHO03 | APS Fast Orbit Feedback System Upgrade | 1301 |
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Funding: * Work supported by U.S. Department of Energy, Office of Science, under Contract No. DE-AC02-06CH11357. A real-time feedback double sector controller (RTFB DSC) for the APS Upgrade has been under design for the past year. Using the Xilinx Zynq-7000 All Programmable System on a Chip FPGA residing on the ZC706 board as the base platform, the upgrade path interfaces to the existing accelerator system and modernizes the beam position monitoring and feedback systems. The modernized system increases the RTFB system sample rate from 1.5 kHz to 22.6 kHz. We report the plan for sector-by-sector upgrades that will occur during system shutdowns and allow the upgraded sectors to operate with the existing sectors. The mapping of the RTFB DSC architecture is shown utilizing the targeted FPGA features. These features include the dual ARM CortexTM-A9 processors, multi-port DDR3 memory controllers, gigabit transceivers, and the programming logic interconnect for implementing advanced orbit feedback controller algorithms using floating-point DSP operations. The RTFB DSC FPGA architecture is revealed as well as subsequent progress on the chassis implementation. |
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