PAC2013 - List of Authors (Bui, H.)

Paper	Title	Page
THPAC08	Modernization of the Bergoz Multiplexed BPM System for the APS Upgrade	1154
	X. Sun, H. Bui, G. Decker, R.T. Keane, R.M. Lill, B.X. Yang ANL, Argonne, USA
	Funding: * Work supported by U.S. Department of Energy, Office of Science, under Contract No. DE-AC02-06CH11357 The APS upgrade includes improvements to the Bergoz Multiplexed BPM system, which presently suffers from an aging data acquisition system. The upgrade leverages off the development of an eight-channel data acquisition system featuring modern FPGA flexibility that was designed for the monopulse BPM system. This upgrade also provides an external clock signal synchronized to the APS revolution clock that will eliminate the aliasing caused by the Bergoz asynchronous multiplexing interacting with different accelerator fill patterns. The upgrade will revitalize this system and demonstrate a cost-effective approach to improved beam stability, reliability, and enhanced postmortem capabilities. In this paper we will discuss the upgrade system specifications, design, and prototype test results.

THPHO03	APS Fast Orbit Feedback System Upgrade	1301
	R. Lipa, N.D. Arnold, H. Bui, G. Decker, T. Fors, R. Laird, F. Lenkszus, A.J. Scaminaci, N. Sereno, S.E. Shoaf ANL, Argonne, USA
	Funding: * Work supported by U.S. Department of Energy, Office of Science, under Contract No. DE-AC02-06CH11357. A real-time feedback double sector controller (RTFB DSC) for the APS Upgrade has been under design for the past year. Using the Xilinx Zynq-7000 All Programmable System on a Chip FPGA residing on the ZC706 board as the base platform, the upgrade path interfaces to the existing accelerator system and modernizes the beam position monitoring and feedback systems. The modernized system increases the RTFB system sample rate from 1.5 kHz to 22.6 kHz. We report the plan for sector-by-sector upgrades that will occur during system shutdowns and allow the upgraded sectors to operate with the existing sectors. The mapping of the RTFB DSC architecture is shown utilizing the targeted FPGA features. These features include the dual ARM CortexTM-A9 processors, multi-port DDR3 memory controllers, gigabit transceivers, and the programming logic interconnect for implementing advanced orbit feedback controller algorithms using floating-point DSP operations. The RTFB DSC FPGA architecture is revealed as well as subsequent progress on the chassis implementation.

Paper

Title

Page

Modernization of the Bergoz Multiplexed BPM System for the APS Upgrade

1154

X. Sun, H. Bui, G. Decker, R.T. Keane, R.M. Lill, B.X. Yang
ANL, Argonne, USA

Funding: * Work supported by U.S. Department of Energy, Office of Science, under Contract No. DE-AC02-06CH11357
The APS upgrade includes improvements to the Bergoz Multiplexed BPM system, which presently suffers from an aging data acquisition system. The upgrade leverages off the development of an eight-channel data acquisition system featuring modern FPGA flexibility that was designed for the monopulse BPM system. This upgrade also provides an external clock signal synchronized to the APS revolution clock that will eliminate the aliasing caused by the Bergoz asynchronous multiplexing interacting with different accelerator fill patterns. The upgrade will revitalize this system and demonstrate a cost-effective approach to improved beam stability, reliability, and enhanced postmortem capabilities. In this paper we will discuss the upgrade system specifications, design, and prototype test results.

THPHO03

APS Fast Orbit Feedback System Upgrade

1301

R. Lipa, N.D. Arnold, H. Bui, G. Decker, T. Fors, R. Laird, F. Lenkszus, A.J. Scaminaci, N. Sereno, S.E. Shoaf
ANL, Argonne, USA

Funding: * Work supported by U.S. Department of Energy, Office of Science, under Contract No. DE-AC02-06CH11357.
A real-time feedback double sector controller (RTFB DSC) for the APS Upgrade has been under design for the past year. Using the Xilinx Zynq-7000 All Programmable System on a Chip FPGA residing on the ZC706 board as the base platform, the upgrade path interfaces to the existing accelerator system and modernizes the beam position monitoring and feedback systems. The modernized system increases the RTFB system sample rate from 1.5 kHz to 22.6 kHz. We report the plan for sector-by-sector upgrades that will occur during system shutdowns and allow the upgraded sectors to operate with the existing sectors. The mapping of the RTFB DSC architecture is shown utilizing the targeted FPGA features. These features include the dual ARM CortexTM-A9 processors, multi-port DDR3 memory controllers, gigabit transceivers, and the programming logic interconnect for implementing advanced orbit feedback controller algorithms using floating-point DSP operations. The RTFB DSC FPGA architecture is revealed as well as subsequent progress on the chassis implementation.