• T.A. Butler, L.J. Allen, J. Branlard, B. Chase, E. Cullerton, P.W. Joireman, M.J. Kucera, V. Tupikov, P. Varghese
  Fermilab, Batavia

The Fermilab Proton Plan, tasked to increase the intensity and reliability of the Proton Source, has identified the Low Level RF (LLRF) system as the critical component to be upgraded in the Linac. The current 201.25 MHz Drift Tube Linac LLRF system was designed and built over 35 years ago and does not meet the higher beam quality requirements under the new Proton Plan. A new VXI based LLRF system has been designed to improve cavity vector regulation and reduce beam losses. The upgrade includes an adaptive feedforward system for beam loading compensation, a new phase feedback system, and a digital phase comparator for cavity tuning. The new LLRF system is phase locked to a temperature stabilized 805 MHz reference line, currently used as frequency standard in the higher energy accelerating section of the Linac. This paper will address the current status of the project, present the advancements in both amplitude and phase stability over the old LLRF system, and discuss commissioning plans.

• U. Mavric, B. Barnes, J. Branlard, B. Chase, D.W. Klepec, V. Tupikov
  Fermilab, Batavia

Funding: Work supported by Fermi Research Alliance LLC. Under DE-AC02- 07CH11359 with the U.S. DOE
The proposed 30 km long ILC electron/positron collider is pushing the limits not only in basic physics research but also in engineering. For the two main Linacs, the pulsed rf power that is feeding the high number of SCRF cavities (~17,000) must to be regulated to app. 0.1% for amplitude and 0.2 deg for phase. The regulation of phase and amplitude is carried out by the analog/digital electronics also denoted as the low-level rf control system. Besides meeting the regulation specifications, the low-level rf must be reliable, robust and low cost. In the paper we present a possible hardware solution that addresses these issues. We also reveal the main design strategies that allowed us meeting the conflicting demands of the system. The system is evaluated on a cavity emulator implemented on the FPGA, which shows that system performance is within the specifications. Finally, we discuss the obtained results and give some suggestions for future work.