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Funding: Department of Atomic Energy, India.
CERN is building a 352.2 MHz, 3 MeV RFQ based Test Stand as first part of LINAC 4. Extending its collaboration with DAE of India, CERN approached us to design and develop a high voltage pulsed modulator for 1 MW LEP klystrons (planning their reuse). Three design schemes were proposed out of which an all solid state bouncer compensated modulator was chosen for follow up development. The main features of the modulator are: no gas tube crow-bar, all solid state construction low rise/fall times and high stability of the flat top. The major specifications are output voltage upto 110 kV, output current upto 24 Amp, pulse duration 800 μs, PRR 2Hz, pulse droop <1% and ripple on pulse top <0.1%. The energy in klystron arc is restricted to 10J. Based on these principles, a modulator has been developed and constructed at CERN and is currently undergoing tests with a klystron while another one with similar development is in the final stages of integration/evaluation at RRCAT. The present paper describes the topology, simulation results, protection strategy and integration aspects of the pulse modulator and would briefly summarize the results.
The work is done under DAE CERN Collaboration under NAT Protocol.
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