ICALEPCS2017 - List of Authors (Rujanakraikarn, R.)

Paper	Title	Page
TUPHA068	FPGA-Based Pulsed-RF Phase and Amplitude Detector at SLRI	557
	R. Rujanakraikarn SLRI, Nakhon Ratchasima, Thailand
	In this paper, the prototype of phase and amplitude detector for pulsed-RF measurement is described. The hardware is designed in VHDL and implemented using Field Programmable Gate Array (FPGA) for digital processing. The main phase and amplitude detection algorithm is implemented using state machine in the MicroBlaze soft processor. The detector system is designed to measure the phase and amplitude of a 5-microsecond wide 2,856 MHz pulsed-RF at a repetition rate of 0.5 Hz. The front-end hardware for the pulsed-RF signal acquisition is also described with the interface to the FPGA-based controller part. Initial test results of the prototype are presented.
	Poster TUPHA068 [3.645 MB]
DOI •	reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2017-TUPHA068
Export •	reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

TUPHA069	FPGA-Based Motion Control System for Medical Linear Accelerator Development at SLRI	562
	R. Rujanakraikarn, P. Koonpong SLRI, Nakhon Ratchasima, Thailand
	Linear accelerator technology has been widely applied to radiotherapy machines and there has been an increasing demand of the machines in Thailand over the recent years. An attempt to increase the availability of the low-cost machines has been proposed for the domestic use purposes. Currently, the prototype of the 6 MeV medical linear accelerator is under development at Synchrotron Light Research Institute (SLRI) in Nakorn Ratchasima, Thailand. For beam shaping purposes a so-called secondary collimator is utilized with different size arrangement of the collimator jaws. The collimator motion control is one of the necessary machine subsystems for producing the desired field size of the beam. In this paper, the FPGA-based motion control system of the machine prototype is presented. The programmable logic part of the hardware is designed in VHDL for digital processing. The main motion control algorithm is implemented in the main processor of Zedboard FPGA. Communication between the motion control subsystem and the main control system software of the machine is also described.
	Poster TUPHA069 [4.103 MB]
DOI •	reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2017-TUPHA069
Export •	reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

TUPHA079	Timing System Using FPGA for Medical Linear Accelerator Prototype at SLRI	589
	P. Koonpong, R. Rujanakraikarn SLRI, Nakhon Ratchasima, Thailand
	A prototype of medical linear accelerator is under development at Synchrotron Light Research Institute (SLRI). In order to maintain the proper operation of the machine, the pulse signal is used to synchronize the various subsystems such as electron gun, RF trigger, and magnetron trigger subsystems. In this project, we design the timing system using a XilinxSpartan-3 FPGA development board with VHDL in order to achieve the desired characteristics and sequences of the timing signals for those subsystems. A LabVIEW GUI is designed to interface with the timing system in order to control the time delay and pulse width via RS-232 serial interface. The results of the system design is achieved with the pulse resolution of a 20 nsec per step for four timing channels. The time delay and pulse width for each channel can be set independently based on the SYNC reference signal.
	Poster TUPHA079 [3.417 MB]
DOI •	reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2017-TUPHA079
Export •	reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

Paper

Title

Page

FPGA-Based Pulsed-RF Phase and Amplitude Detector at SLRI

557

R. Rujanakraikarn
SLRI, Nakhon Ratchasima, Thailand

In this paper, the prototype of phase and amplitude detector for pulsed-RF measurement is described. The hardware is designed in VHDL and implemented using Field Programmable Gate Array (FPGA) for digital processing. The main phase and amplitude detection algorithm is implemented using state machine in the MicroBlaze soft processor. The detector system is designed to measure the phase and amplitude of a 5-microsecond wide 2,856 MHz pulsed-RF at a repetition rate of 0.5 Hz. The front-end hardware for the pulsed-RF signal acquisition is also described with the interface to the FPGA-based controller part. Initial test results of the prototype are presented.

Poster TUPHA068 [3.645 MB]

DOI •

reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2017-TUPHA068

Export •

reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

TUPHA069

FPGA-Based Motion Control System for Medical Linear Accelerator Development at SLRI

562

R. Rujanakraikarn, P. Koonpong
SLRI, Nakhon Ratchasima, Thailand

Linear accelerator technology has been widely applied to radiotherapy machines and there has been an increasing demand of the machines in Thailand over the recent years. An attempt to increase the availability of the low-cost machines has been proposed for the domestic use purposes. Currently, the prototype of the 6 MeV medical linear accelerator is under development at Synchrotron Light Research Institute (SLRI) in Nakorn Ratchasima, Thailand. For beam shaping purposes a so-called secondary collimator is utilized with different size arrangement of the collimator jaws. The collimator motion control is one of the necessary machine subsystems for producing the desired field size of the beam. In this paper, the FPGA-based motion control system of the machine prototype is presented. The programmable logic part of the hardware is designed in VHDL for digital processing. The main motion control algorithm is implemented in the main processor of Zedboard FPGA. Communication between the motion control subsystem and the main control system software of the machine is also described.

Poster TUPHA069 [4.103 MB]

DOI •

reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2017-TUPHA069

Export •

reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

TUPHA079

Timing System Using FPGA for Medical Linear Accelerator Prototype at SLRI

589

P. Koonpong, R. Rujanakraikarn
SLRI, Nakhon Ratchasima, Thailand

A prototype of medical linear accelerator is under development at Synchrotron Light Research Institute (SLRI). In order to maintain the proper operation of the machine, the pulse signal is used to synchronize the various subsystems such as electron gun, RF trigger, and magnetron trigger subsystems. In this project, we design the timing system using a XilinxSpartan-3 FPGA development board with VHDL in order to achieve the desired characteristics and sequences of the timing signals for those subsystems. A LabVIEW GUI is designed to interface with the timing system in order to control the time delay and pulse width via RS-232 serial interface. The results of the system design is achieved with the pulse resolution of a 20 nsec per step for four timing channels. The time delay and pulse width for each channel can be set independently based on the SYNC reference signal.

Poster TUPHA079 [3.417 MB]

DOI •

reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2017-TUPHA079

Export •

reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)