ICALEPCS2017 - List of Authors (Daniluk, G.)

Paper	Title	Page
TUAPL03	Solving Vendor Lock-in in VME Single Board Computers through Open-sourcing of the PCIe-VME64x Bridge	131
	G. Daniluk, J.D. Gonzalez Cobas, M. Suminski, A. Wujek CERN, Geneva, Switzerland G. Gräbner, M. Miehling, T. Schnürer MEN, Nürnberg, Germany
	VME is a standard for modular electronics widely used in research institutes. Slave cards in a VME crate are controlled from a VME master, typically part of a Single Board Computer (SBC). The SBC typically runs an operating system and communicates with the VME bus through a PCI or PCIe-to-VME bridge chip. The de-facto standard bridge, TSI148, has recently been discontinued, and therefore the question arises about what bridging solution to use in new commercial SBC designs. This paper describes our effort to solve the VME bridge availability problem. Together with a commercial company, MEN, we have open-sourced their VHDL implementation of the PCIe-VME64x interface. We have created a new commodity which is free to be used in any SBC having an FPGA, thus avoiding vendor lock-in and providing a fertile ground for collaboration among institutes and companies around the VME platform. The article also describes the internals of the MEN PCIe-VME64x HDL core as well as the software package that comes with it.
	Talk as video stream: https://youtu.be/rEbUntNO-_Q
	Slides TUAPL03 [15.891 MB]
DOI •	reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2017-TUAPL03
Export •	reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

TUSH303	Managing your Timing System as a Standard Ethernet Network	1007
	A. Wujek, G. Daniluk, M.M. Lipinski CERN, Geneva, Switzerland A. Rubini GNUDD, Pavia, Italy
	White Rabbit (WR) is an extension of Ethernet which allows deterministic data delivery and remote synchronization of nodes with accuracies below 1 nanosecond and jitter better than 10 ps. Because WR is Ethernet, a WR-based timing system can benefit from all standard network protocols and tools available in the Ethernet ecosystem. This paper describes the configuration, monitoring and diagnostics of a WR network using standard tools. Using the Simple Network Management Protocol (SNMP), clients can easily monitor with standard monitoring tools like Nagios, Icinga and Grafana e.g. the quality of the data link and synchronization. The former involves e.g. the number of dropped frames; The latter concerns parameters such as the latency of frame distribution and fibre delay compensation. The Link Layer Discovery Protocol (LLDP) allows discovery of the actual topology of a network. Wireshark and PTP Track Hound can intercept and help with analysis of the content of WR frames of live traffic. In order to benefit from time-proven, scalable, standard monitoring solutions, some development was needed in the WR switch and nodes.
	Poster TUSH303 [1.608 MB]
DOI •	reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2017-TUSH303
Export •	reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

THPHA071	Plans at CERN for Electronics and Communication in the Distributed I/O Tier	1552
	G. Daniluk, E. Gousiou CERN, Geneva, Switzerland
	Controls and data acquisition in accelerators often involve some kind of computing platform (VME, PICMG 1.3, MTCA.4…) connected to Distributed I/O Tier electronics using a fieldbus or another kind of serial link. At CERN, we have started a project to rationalize this tier, providing a modular centrally-supported platform which allows equipment groups to focus on solving their particular problems while benefiting from a set of well-debugged building blocks. The paper describes the strategy, based on 3U Euro crates with a generic FPGA-based board featuring space for FMC mezzanines. Different mezzanines allow communication using different protocols. There are two variants of the electronics, to deploy in environments with and without radiation tolerance requirements. The plans we present are the result of extensive discussion at CERN among all stakeholders. We present them here with the aim of gathering further feedback and potential interest for inter-lab collaborations.
	Poster THPHA071 [3.171 MB]
DOI •	reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2017-THPHA071
Export •	reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

Paper

Title

Page

Solving Vendor Lock-in in VME Single Board Computers through Open-sourcing of the PCIe-VME64x Bridge

131

G. Daniluk, J.D. Gonzalez Cobas, M. Suminski, A. Wujek
CERN, Geneva, Switzerland
G. Gräbner, M. Miehling, T. Schnürer
MEN, Nürnberg, Germany

VME is a standard for modular electronics widely used in research institutes. Slave cards in a VME crate are controlled from a VME master, typically part of a Single Board Computer (SBC). The SBC typically runs an operating system and communicates with the VME bus through a PCI or PCIe-to-VME bridge chip. The de-facto standard bridge, TSI148, has recently been discontinued, and therefore the question arises about what bridging solution to use in new commercial SBC designs. This paper describes our effort to solve the VME bridge availability problem. Together with a commercial company, MEN, we have open-sourced their VHDL implementation of the PCIe-VME64x interface. We have created a new commodity which is free to be used in any SBC having an FPGA, thus avoiding vendor lock-in and providing a fertile ground for collaboration among institutes and companies around the VME platform. The article also describes the internals of the MEN PCIe-VME64x HDL core as well as the software package that comes with it.

Talk as video stream: https://youtu.be/rEbUntNO-_Q

Slides TUAPL03 [15.891 MB]

DOI •

reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2017-TUAPL03

Export •

reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

TUSH303

Managing your Timing System as a Standard Ethernet Network

1007

A. Wujek, G. Daniluk, M.M. Lipinski
CERN, Geneva, Switzerland
A. Rubini
GNUDD, Pavia, Italy

White Rabbit (WR) is an extension of Ethernet which allows deterministic data delivery and remote synchronization of nodes with accuracies below 1 nanosecond and jitter better than 10 ps. Because WR is Ethernet, a WR-based timing system can benefit from all standard network protocols and tools available in the Ethernet ecosystem. This paper describes the configuration, monitoring and diagnostics of a WR network using standard tools. Using the Simple Network Management Protocol (SNMP), clients can easily monitor with standard monitoring tools like Nagios, Icinga and Grafana e.g. the quality of the data link and synchronization. The former involves e.g. the number of dropped frames; The latter concerns parameters such as the latency of frame distribution and fibre delay compensation. The Link Layer Discovery Protocol (LLDP) allows discovery of the actual topology of a network. Wireshark and PTP Track Hound can intercept and help with analysis of the content of WR frames of live traffic. In order to benefit from time-proven, scalable, standard monitoring solutions, some development was needed in the WR switch and nodes.

Poster TUSH303 [1.608 MB]

DOI •

reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2017-TUSH303

Export •

reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

THPHA071

Plans at CERN for Electronics and Communication in the Distributed I/O Tier

1552

G. Daniluk, E. Gousiou
CERN, Geneva, Switzerland

Controls and data acquisition in accelerators often involve some kind of computing platform (VME, PICMG 1.3, MTCA.4…) connected to Distributed I/O Tier electronics using a fieldbus or another kind of serial link. At CERN, we have started a project to rationalize this tier, providing a modular centrally-supported platform which allows equipment groups to focus on solving their particular problems while benefiting from a set of well-debugged building blocks. The paper describes the strategy, based on 3U Euro crates with a generic FPGA-based board featuring space for FMC mezzanines. Different mezzanines allow communication using different protocols. There are two variants of the electronics, to deploy in environments with and without radiation tolerance requirements. The plans we present are the result of extensive discussion at CERN among all stakeholders. We present them here with the aim of gathering further feedback and potential interest for inter-lab collaborations.

Poster THPHA071 [3.171 MB]

DOI •

reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2017-THPHA071

Export •

reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)