ICALEPCS2017 - List of Authors (Allison, T.L.)

Paper	Title	Page
TUMPL03	New EPICS/RTEMS IOC Based on Altera SOC at Jefferson Lab	304
	J. Yan, T.L. Allison, B. Bevins, A. Cuffe, C. Seaton JLab, Newport News, Virginia, USA
	A new EPICS/RTEMS IOC based on the Altera System-on-Chip (SoC) FPGA was designed at Jefferson Lab. The Altera SoC FPGA integrates a dual ARM Cortex-A9 hard processor system (HPS) consisting of processor, peripherals and memory interfaces tied seamlessly with the FPGA fabric using a high-bandwidth interconnect backbone. The embedded Altera SoC IOC has features of remote network boot via u-boot from SD card or QSPI Flash, 1Gig Ethernet, 1GB DDRs SDRAM on HPS, UART serial ports, and ISA bus interface. RTEMS for the ARM processor BSP were built with CEXP shell, which will dynamically load the EPICS applications at runtime. U-boot is the primary bootloader to remotely load the kernel image into local memory from a DHCP/TFTP server over Ethernet, and automatically run the RTEMS and EPICS. The standard SoC IOC board would be mounted in a chassis and connected to a daughter card via a standard HSMC connector. The first design of the SoC IOC will be compatible with our current PC10⁴ IOCs, which have been running on our accelerator control system for 10 years. Eventually, the standard SOC IOCS would be the next generation of low-level IOC for the Accelerator control at Jefferson Lab. Authored by Jefferson Science Associates, LLC under U.S. DOE Contract No. DE-AC05-06OR23177.
	Slides TUMPL03 [1.094 MB]
DOI •	reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2017-TUMPL03
Export •	reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

Paper

Title

Page

New EPICS/RTEMS IOC Based on Altera SOC at Jefferson Lab

304

J. Yan, T.L. Allison, B. Bevins, A. Cuffe, C. Seaton
JLab, Newport News, Virginia, USA

A new EPICS/RTEMS IOC based on the Altera System-on-Chip (SoC) FPGA was designed at Jefferson Lab. The Altera SoC FPGA integrates a dual ARM Cortex-A9 hard processor system (HPS) consisting of processor, peripherals and memory interfaces tied seamlessly with the FPGA fabric using a high-bandwidth interconnect backbone. The embedded Altera SoC IOC has features of remote network boot via u-boot from SD card or QSPI Flash, 1Gig Ethernet, 1GB DDRs SDRAM on HPS, UART serial ports, and ISA bus interface. RTEMS for the ARM processor BSP were built with CEXP shell, which will dynamically load the EPICS applications at runtime. U-boot is the primary bootloader to remotely load the kernel image into local memory from a DHCP/TFTP server over Ethernet, and automatically run the RTEMS and EPICS. The standard SoC IOC board would be mounted in a chassis and connected to a daughter card via a standard HSMC connector. The first design of the SoC IOC will be compatible with our current PC10⁴ IOCs, which have been running on our accelerator control system for 10 years. Eventually, the standard SOC IOCS would be the next generation of low-level IOC for the Accelerator control at Jefferson Lab.
Authored by Jefferson Science Associates, LLC under U.S. DOE Contract No. DE-AC05-06OR23177.

Slides TUMPL03 [1.094 MB]

DOI •

reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2017-TUMPL03

Export •

reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)