IBIC2014 - List of Authors (Zhao, L.Y.)

Paper	Title	Page
MOPD23	Development Status of SINAP Timing System	199
	M. Liu, K.C. Chu, C.X. Yin, L.Y. Zhao SINAP, Shanghai, People's Republic of China
	After successful implementation of SINAP timing solution at Pohang Light Source in 2011, we started to upgrade SINAP timing system to version 2. The hardware of SINAP v2 timing system is based on Virtex-6 FPGA chip, and bidirectional event frame transfer is realized in a 2.5Gbps fiber-optic network. In event frame, data transfer functionality substitutes for distributed bus. The structure of timing system is also modified, where a new versatile EVO could be configured as EVG, FANOUT or EVR with optical outputs. Besides standard VME modules, we designed PLC-EVR as well, which is compatible with Yokogawa F3RP61 series. Based on brand new hardware architecture, the jitter performance of SINAP v2 timing system is improved remarkably.
	Poster MOPD23 [4.282 MB]
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Paper

Title

Page

Development Status of SINAP Timing System

199

M. Liu, K.C. Chu, C.X. Yin, L.Y. Zhao
SINAP, Shanghai, People's Republic of China

After successful implementation of SINAP timing solution at Pohang Light Source in 2011, we started to upgrade SINAP timing system to version 2. The hardware of SINAP v2 timing system is based on Virtex-6 FPGA chip, and bidirectional event frame transfer is realized in a 2.5Gbps fiber-optic network. In event frame, data transfer functionality substitutes for distributed bus. The structure of timing system is also modified, where a new versatile EVO could be configured as EVG, FANOUT or EVR with optical outputs. Besides standard VME modules, we designed PLC-EVR as well, which is compatible with Yokogawa F3RP61 series. Based on brand new hardware architecture, the jitter performance of SINAP v2 timing system is improved remarkably.

Poster MOPD23 [4.282 MB]

Export •

reference for this paper to ※ LaTeX, ※ Text, ※ IS/RefMan, ※ EndNote (xml)