TY - CPAPER
AU - Liu, M.
AU - Chu, K.C.
AU - Yin, C.X.
AU - Zhao, L.Y.
TI - Development Status of SINAP Timing System
J2 - Proc. of IBIC2014
AB - After successful implementation of SINAP timing solution at Pohang Light Source in 2011, we started to upgrade SINAP timing system to version 2. The hardware of SINAP v2 timing system is based on Virtex-6 FPGA chip, and bidirectional event frame transfer is realized in a 2.5Gbps fiber-optic network. In event frame, data transfer functionality substitutes for distributed bus. The structure of timing system is also modified, where a new versatile EVO could be configured as EVG, FANOUT or EVR with optical outputs. Besides standard VME modules, we designed PLC-EVR as well, which is compatible with Yokogawa F3RP61 series. Based on brand new hardware architecture, the jitter performance of SINAP v2 timing system is improved remarkably.
PB - JACoW
CY - Geneva, Switzerland
SP - 199
EP - 201
KW - timing
KW - FPGA
KW - software
KW - network
KW - PLC
DA - 2014/10
PY - 2014
SN - 978-3-95450-141-0
UR - http://jacow.org/IBIC2014/papers/mopd23.pdf
ER -