ICALEPCS2019 - List of Authors (Stettler, M.W.)

Paper	Title	Page
THCPR03	A Safety Rated FPGA Framework for Fast Safety Systems	1626
	F. Tao, B.M. Bennett, D.G. Brown, J. Jones, M.W. Stettler SLAC, Menlo Park, California, USA
	In this paper, we will introduce a generic safety-rated FPGA design template. FMEDA analysis, hardware reliability modeling, firmware development, verification and validation will be described in details to demonstrate the IEC 61508 compliant development process. In this dual redundant design, each chain consists a FPGA chip from different manufacturers to minimize the potential common cause failures. Cross checks between FPGAs and end-to-end self-checks are performed to increase the diagnostic coverage and improve the reliability. Based on this safety FPGA template, an Average Current Monitor (ACM) system is developed at SLAC with the addition of a safety PLC for diagnostics and a HMI for user interface. The overall system is deployed as part of Beam Containment System (BCS) to limit the beam current with the target Safety Integrity Level (SIL) 2.
DOI •	reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2019-THCPR03
About •	paper received ※ 01 October 2019 paper accepted ※ 08 October 2019 issue date ※ 30 August 2020
Export •	reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

Paper

Title

Page

A Safety Rated FPGA Framework for Fast Safety Systems

1626

F. Tao, B.M. Bennett, D.G. Brown, J. Jones, M.W. Stettler
SLAC, Menlo Park, California, USA

In this paper, we will introduce a generic safety-rated FPGA design template. FMEDA analysis, hardware reliability modeling, firmware development, verification and validation will be described in details to demonstrate the IEC 61508 compliant development process. In this dual redundant design, each chain consists a FPGA chip from different manufacturers to minimize the potential common cause failures. Cross checks between FPGAs and end-to-end self-checks are performed to increase the diagnostic coverage and improve the reliability. Based on this safety FPGA template, an Average Current Monitor (ACM) system is developed at SLAC with the addition of a safety PLC for diagnostics and a HMI for user interface. The overall system is deployed as part of Beam Containment System (BCS) to limit the beam current with the target Safety Integrity Level (SIL) 2.

DOI •

reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2019-THCPR03

About •

paper received ※ 01 October 2019 paper accepted ※ 08 October 2019 issue date ※ 30 August 2020

Export •

reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)