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@InProceedings{tao:icalepcs2019-thcpr03,
author = {F. Tao and B.M. Bennett and D.G. Brown and J. Jones and M.W. Stettler},
title = {{A Safety Rated FPGA Framework for Fast Safety Systems}},
booktitle = {Proc. ICALEPCS'19},
pages = {1626--1629},
paper = {THCPR03},
language = {english},
keywords = {FPGA, PLC, electron, hardware, diagnostics},
venue = {New York, NY, USA},
series = {International Conference on Accelerator and Large Experimental Physics Control Systems},
number = {17},
publisher = {JACoW Publishing, Geneva, Switzerland},
month = {08},
year = {2020},
issn = {2226-0358},
isbn = {978-3-95450-209-7},
doi = {10.18429/JACoW-ICALEPCS2019-THCPR03},
url = {https://jacow.org/icalepcs2019/papers/thcpr03.pdf},
note = {https://doi.org/10.18429/JACoW-ICALEPCS2019-THCPR03},
abstract = {In this paper, we will introduce a generic safety-rated FPGA design template. FMEDA analysis, hardware reliability modeling, firmware development, verification and validation will be described in details to demonstrate the IEC 61508 compliant development process. In this dual redundant design, each chain consists a FPGA chip from different manufacturers to minimize the potential common cause failures. Cross checks between FPGAs and end-to-end self-checks are performed to increase the diagnostic coverage and improve the reliability. Based on this safety FPGA template, an Average Current Monitor (ACM) system is developed at SLAC with the addition of a safety PLC for diagnostics and a HMI for user interface. The overall system is deployed as part of Beam Containment System (BCS) to limit the beam current with the target Safety Integrity Level (SIL) 2.},
}