ICALEPCS2019 - List of Authors (Fustier, A.)

Paper	Title	Page
TUBPR02	A 4-Channel, 7 ns-Delay Tuning Range, 400 fs-Step, 1.8 ps RMS Jitter, Delay Generator Implemented in a 180 nm CMOS Technology	733
	F.C. Badets, G.A. Billiot, S. Bouquet, B. Caillat, A. Fustier, F. Lepin, C. Magnier, G. Regis, A. Spataro CEA, Grenoble, France D. Monnier-Bourdin, B. Riondet Greenfield Technology, Breuillet, France
	This paper discloses the integration, in a 180 nm CMOS technology, of a 4-channel delay generator dedicated to synchronization down to a few ps. The delay generation principle relies on the linear charge of a capacitor triggered by the input pulse. The output pulse generation occurs when the capacitor voltage exceeds a threshold voltage. The delay full scale is automatically set to match the period of the master clock, ranging from 5-7 ns, with the help of an embedded calibration circuit. The delay value is controlled with the help of a 14-bit DAC setting the threshold voltage, which leads to a 400 fs delay step. Among other features, the chip embeds a combination mode of either 2 or 4 channels to output narrow width pulses. The chip is fully compliant with LVDS, LVPECL and CML differential input pulses and outputs LVPECL pulses. The chip has been fully characterized over temperature (0 to 60 °C) and supply voltage (± 10%). The chip is compliant with pulse repetition frequencies up to 20 MHz. The measured INL is 100 LSB and the RMS jitter is 1.8 ps. The power consumption has been measured to 350 mW for 4 active channels.
	Slides TUBPR02 [5.312 MB]
DOI •	reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2019-TUBPR02
About •	paper received ※ 30 September 2019 paper accepted ※ 09 October 2019 issue date ※ 30 August 2020
Export •	reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

Paper

Title

Page

A 4-Channel, 7 ns-Delay Tuning Range, 400 fs-Step, 1.8 ps RMS Jitter, Delay Generator Implemented in a 180 nm CMOS Technology

733

F.C. Badets, G.A. Billiot, S. Bouquet, B. Caillat, A. Fustier, F. Lepin, C. Magnier, G. Regis, A. Spataro
CEA, Grenoble, France
D. Monnier-Bourdin, B. Riondet
Greenfield Technology, Breuillet, France

This paper discloses the integration, in a 180 nm CMOS technology, of a 4-channel delay generator dedicated to synchronization down to a few ps. The delay generation principle relies on the linear charge of a capacitor triggered by the input pulse. The output pulse generation occurs when the capacitor voltage exceeds a threshold voltage. The delay full scale is automatically set to match the period of the master clock, ranging from 5-7 ns, with the help of an embedded calibration circuit. The delay value is controlled with the help of a 14-bit DAC setting the threshold voltage, which leads to a 400 fs delay step. Among other features, the chip embeds a combination mode of either 2 or 4 channels to output narrow width pulses. The chip is fully compliant with LVDS, LVPECL and CML differential input pulses and outputs LVPECL pulses. The chip has been fully characterized over temperature (0 to 60 °C) and supply voltage (± 10%). The chip is compliant with pulse repetition frequencies up to 20 MHz. The measured INL is 100 LSB and the RMS jitter is 1.8 ps. The power consumption has been measured to 350 mW for 4 active channels.

Slides TUBPR02 [5.312 MB]

DOI •

reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2019-TUBPR02

About •

paper received ※ 30 September 2019 paper accepted ※ 09 October 2019 issue date ※ 30 August 2020

Export •

reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)