PCaPAC2012 - List of Authors (Rauch, S.)

Paper

Title

Page

Facility-Wide Synchronization of Standard FAIR Equipment Controllers

84

S. Rauch, R. Bär, D.H. Beck, M. Kreider, W. Panschow, C. Prados, W.W. Terpstra, M. Thieme, M. Zweig
GSI, Darmstadt, Germany

The standard equipment controller for the new FAIR accelerator facility is the Scalable Control Unit (SCU). It synchronizes and controls the actions of up to 12 purpose-built slave cards, connected in a crate. Facility-wide synchronization is a core FAIR requirement and thus precise timing of SCU slave actions is of vital importance. The SCU consists primarily of two components, a daughter board with CPU and a carrier board with FPGA, interconnected by PCI Express. The CPU receives configuration and set values with which it programs the real-time event-condition-action (ECA) unit in the FPGA. The ECA unit receives event messages via the timing network, which also synchronizes clocks using White Rabbit. Matching events trigger actions on the SCU slave cards such as ramping magnets, triggering kickers, etc. Timing requirements differ depending on the action taken. For softer real-time actions, an interrupt can be generated for complex processing on the CPU. Alternatively, the FPGA can directly fire a pulse or bus operation. The delay and jitter achievable in each case differs and this paper examines their timing performance to determine which is appropriate for the required actions.

Poster WEPD48 [0.138 MB]

FRIA01

The New White Rabbit Based Timing System for the FAIR Facility

242

D.H. Beck, R. Bär, M. Kreider, C. Prados, S. Rauch, W.W. Terpstra, M. Zweig
GSI, Darmstadt, Germany

A new timestamp and event distribution system for the upcoming FAIR facility is being developed at GSI. This timing system is based on White Rabbit[1], which is a fully deterministic Ethernet-based network for general data transfer and synchronization. White Rabbit is developed by CERN, GSI and other institutes as well as partners from industry based on Synchronous Ethernet and PTP. The main tasks of the FAIR timing system are time synchronization of more than 2000 nodes with nanosecond accuracy, distribution of timing messages and subsequent generation of real-time actions (interrupts, digital signals …) by the nodes of the timing system. This allows precise real-time control of the accelerator equipment according to the beam production schedule. Furthermore the timing system must support other accelerator systems like post-mortem and interlock. It also provides interfaces between the accelerator control system and experiments at FAIR. This contribution focuses on the design principles of the timing system, its integration with other components of the control system, the present status and the planned implementation.
[1] J. Serrano, P. Alvarez, M. Cattin, E. G. Cota, P. M. J. H. Lewis, T. Włostowski et al., The White Rabbit Project, in Proceedings of ICALEPCS TUC004, Kobe, Japan, 2009.

Slides FRIA01 [5.452 MB]

Paper	Title	Page
WEPD48	Facility-Wide Synchronization of Standard FAIR Equipment Controllers	84
	S. Rauch, R. Bär, D.H. Beck, M. Kreider, W. Panschow, C. Prados, W.W. Terpstra, M. Thieme, M. Zweig GSI, Darmstadt, Germany
	The standard equipment controller for the new FAIR accelerator facility is the Scalable Control Unit (SCU). It synchronizes and controls the actions of up to 12 purpose-built slave cards, connected in a crate. Facility-wide synchronization is a core FAIR requirement and thus precise timing of SCU slave actions is of vital importance. The SCU consists primarily of two components, a daughter board with CPU and a carrier board with FPGA, interconnected by PCI Express. The CPU receives configuration and set values with which it programs the real-time event-condition-action (ECA) unit in the FPGA. The ECA unit receives event messages via the timing network, which also synchronizes clocks using White Rabbit. Matching events trigger actions on the SCU slave cards such as ramping magnets, triggering kickers, etc. Timing requirements differ depending on the action taken. For softer real-time actions, an interrupt can be generated for complex processing on the CPU. Alternatively, the FPGA can directly fire a pulse or bus operation. The delay and jitter achievable in each case differs and this paper examines their timing performance to determine which is appropriate for the required actions.
	Poster WEPD48 [0.138 MB]

FRIA01	The New White Rabbit Based Timing System for the FAIR Facility	242
	D.H. Beck, R. Bär, M. Kreider, C. Prados, S. Rauch, W.W. Terpstra, M. Zweig GSI, Darmstadt, Germany
	A new timestamp and event distribution system for the upcoming FAIR facility is being developed at GSI. This timing system is based on White Rabbit[1], which is a fully deterministic Ethernet-based network for general data transfer and synchronization. White Rabbit is developed by CERN, GSI and other institutes as well as partners from industry based on Synchronous Ethernet and PTP. The main tasks of the FAIR timing system are time synchronization of more than 2000 nodes with nanosecond accuracy, distribution of timing messages and subsequent generation of real-time actions (interrupts, digital signals …) by the nodes of the timing system. This allows precise real-time control of the accelerator equipment according to the beam production schedule. Furthermore the timing system must support other accelerator systems like post-mortem and interlock. It also provides interfaces between the accelerator control system and experiments at FAIR. This contribution focuses on the design principles of the timing system, its integration with other components of the control system, the present status and the planned implementation. [1] J. Serrano, P. Alvarez, M. Cattin, E. G. Cota, P. M. J. H. Lewis, T. Włostowski et al., The White Rabbit Project, in Proceedings of ICALEPCS TUC004, Kobe, Japan, 2009.
	Slides FRIA01 [5.452 MB]