PCaPAC2012 - List of Authors (Jha, K.)

Paper	Title	Page
WEPD10	Embedded CAMAC Controller: Hardware/Software Co-optimization for High Throughput	20
	P.M. Nair, A. Behere, M.P. Diwakar, K. Jha, C.K. Pithawa, P. Sridharan BARC, Trombay, Mumbai, India
	Advances in technology have resulted in availability of low-power, low form-factor embedded PC based modules. The Embedded CAMAC Controller (ECC) is designed with ETX standard Single Board Computer having PC architecture with Ethernet connectivity. The paper highlights the software and hardware design optimizations to meet high throughput requirements of multi-parameter experiments and scan mode accelerator control applications. The QNX based software is designed for high throughput by adopting design strategies like multi-threaded architecture, interrupt-driven data transfer, buffer pool for burst data, zero memory copy, lockless primitives and batched event data transfer to host. The data buffer and all control logic for CAMAC cycle sequencing for LIST mode is implemented entirely in hardware in Field Programmable Gate Array (FPGA). Through this design, sustained throughput of 1.5MBps has been achieved. Also, the host connectivity through Ethernet link enables support for multi-crate configuration, thus providing scalability. The ECC has been installed for accelerator control at FOTIA BARC, Pelletron and LINAC Pelletron TIFR and for multi-parameter experiments at NPD.

Paper

Title

Page

Embedded CAMAC Controller: Hardware/Software Co-optimization for High Throughput

20

P.M. Nair, A. Behere, M.P. Diwakar, K. Jha, C.K. Pithawa, P. Sridharan
BARC, Trombay, Mumbai, India

Advances in technology have resulted in availability of low-power, low form-factor embedded PC based modules. The Embedded CAMAC Controller (ECC) is designed with ETX standard Single Board Computer having PC architecture with Ethernet connectivity. The paper highlights the software and hardware design optimizations to meet high throughput requirements of multi-parameter experiments and scan mode accelerator control applications. The QNX based software is designed for high throughput by adopting design strategies like multi-threaded architecture, interrupt-driven data transfer, buffer pool for burst data, zero memory copy, lockless primitives and batched event data transfer to host. The data buffer and all control logic for CAMAC cycle sequencing for LIST mode is implemented entirely in hardware in Field Programmable Gate Array (FPGA). Through this design, sustained throughput of 1.5MBps has been achieved. Also, the host connectivity through Ethernet link enables support for multi-crate configuration, thus providing scalability. The ECC has been installed for accelerator control at FOTIA BARC, Pelletron and LINAC Pelletron TIFR and for multi-parameter experiments at NPD.