Paper |
Title |
Page |
FRCC01 |
Design of the Data Acquisition System for the Nuclear Physics Experiments at VECC |
268 |
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- P. Dhara, P. Maity, A. Roy, P.S. Roy, P. Singhai
VECC, Kolkata, India
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The beam from K130 room temperature cyclotron is being extensively used for nuclear physics experiments for last three decades. The typical beam energy for the experiments is approximately 7-10MeV/nucleon for heavy ions and 8-20MeV/nucleon for light ions. The number of detectors used, may vary from one channel to few hundreds of detector channels. The proposed detector system for experiments with the superconducting cyclotron may have more than 1200 detector channels,and may be generating more than one million parameters per second. The VME and CAMAC based data acquisition system (DAQ) is being used to cater the experimental needs. The current system has been designed based on various commercially available modules in NIM, CAMAC and VME form factor. This type of setup becomes very complicated to maintain for large number of detectors. Alternatively, the distributed DAQ system based on embedded technology is proposed. The traditional analog processing may be replaced by digital filters based FPGA boards. This paper describes the design of current DAQ system and the status of the proposed scheme for distributed DAQ system with capability of handling heterogeneous detector systems.
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Slides FRCC01 [1.239 MB]
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FRCC04 |
Digital Pulse Processing Techniques for High Resolution Amplitude Measurement of Radiation Detector |
279 |
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- P. Singhai, P. Dhara, A. Roy
VECC, Kolkata, India
- S. Chatterjee
HITK, Kolkata, India
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The digital pulse processing techniques for high resolution amplitude measurement of radiation detector pulse is an effective replacement of expensive and bulky analog processing as the digital domain offers higher channel density and at the same time it is cheaper. We have demonstrated a prototype digital setup with high-speed sampling ADC with sampling frequency of 80-125 MHz followed by series of IIR filters for pulse shaping in a trigger-less acquisition mode. The IIR filters, peak detection algorithm and the data write-out logic was written on VHDL and implemented on FPGA. We used CAMAC as the read out platform. In conjunction with the full hardware implementation we also used a mixed-platform with VME digitizer card with raw-sample read out using C code. The rationale behind this mixed platform is to test out various filter algorithms quickly on C and also to benchmark the performance of the chip level ADCs against the standard commercial digitizer in terms of noise or resolution. The paper describes implementation of both the methods with performance obtained in both the methods.
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Slides FRCC04 [1.248 MB]
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