| Paper | Title | Page |
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| WEPD48 | Facility-Wide Synchronization of Standard FAIR Equipment Controllers | 84 |
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| The standard equipment controller for the new FAIR accelerator facility is the Scalable Control Unit (SCU). It synchronizes and controls the actions of up to 12 purpose-built slave cards, connected in a crate. Facility-wide synchronization is a core FAIR requirement and thus precise timing of SCU slave actions is of vital importance. The SCU consists primarily of two components, a daughter board with CPU and a carrier board with FPGA, interconnected by PCI Express. The CPU receives configuration and set values with which it programs the real-time event-condition-action (ECA) unit in the FPGA. The ECA unit receives event messages via the timing network, which also synchronizes clocks using White Rabbit. Matching events trigger actions on the SCU slave cards such as ramping magnets, triggering kickers, etc. Timing requirements differ depending on the action taken. For softer real-time actions, an interrupt can be generated for complex processing on the CPU. Alternatively, the FPGA can directly fire a pulse or bus operation. The delay and jitter achievable in each case differs and this paper examines their timing performance to determine which is appropriate for the required actions. | ||
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Poster WEPD48 [0.138 MB] | |
| THPD44 | The CS framework as a Control System for the HITRAP Facility at GSI | 219 |
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| At the GSI accelerator complex in Darmstadt Germany the linear decelerator HITRAP is currently under commissioning. The aim is to provide highly charged ions up to bare uranium at cryogenic temperatures for various experiments as for instance tests of the theory of quantum electrodynamics. The ions are delivered with kinetic energies of about 4 MeV/u from GSIs experimental storage ring (ESR) and are slowed down in several steps until they are trapped and cooled down in a Penning trap. Whereas for the ESR as well as for the first sections of the linear decelerator the GSI accelerator control system is used the cooler trap as well as the subsequent transfer section to the experimental area are controlled with the LabVIEW based CS-framework developed at GSI. This framework is an object-oriented, event driven and multi-threaded framework with SCADA functionality, which is currently in use at many different experiments world-wide. For the HITRAP facility additional features like an online beam monitoring, realized with the integration of a LVOOP class capable of reading out IMAQ cameras, as well as a new GUI were implemented, which allows automatic scans of beam elements. | ||
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Poster THPD44 [1.319 MB] | |
| FRIA01 | The New White Rabbit Based Timing System for the FAIR Facility | 242 |
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A new timestamp and event distribution system for the upcoming FAIR facility is being developed at GSI. This timing system is based on White Rabbit[1], which is a fully deterministic Ethernet-based network for general data transfer and synchronization. White Rabbit is developed by CERN, GSI and other institutes as well as partners from industry based on Synchronous Ethernet and PTP. The main tasks of the FAIR timing system are time synchronization of more than 2000 nodes with nanosecond accuracy, distribution of timing messages and subsequent generation of real-time actions (interrupts, digital signals …) by the nodes of the timing system. This allows precise real-time control of the accelerator equipment according to the beam production schedule. Furthermore the timing system must support other accelerator systems like post-mortem and interlock. It also provides interfaces between the accelerator control system and experiments at FAIR. This contribution focuses on the design principles of the timing system, its integration with other components of the control system, the present status and the planned implementation.
[1] J. Serrano, P. Alvarez, M. Cattin, E. G. Cota, P. M. J. H. Lewis, T. Włostowski et al., The White Rabbit Project, in Proceedings of ICALEPCS TUC004, Kobe, Japan, 2009. |
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Slides FRIA01 [5.452 MB] | |