
In the GSI control system a function generator (FG) is used to control equipment with timing functions (ramps). It is situated between the realtime equipment controller (EC) and the actual device control electronics. It provides a 24 bit wide output with an internal accuracy of 32 bits. In ramping mode the FG is configured from the EC with interpolation points. By interpolating the function values the communication on the field bus is minimized. Presently, the interpolation in the FG is linear, which requires only one accumulator of 32 bit width. To better fit the physical functions with less interpolation points we have extended the generator to quadratic interpolation implementing a 2dimensional arithmetic progression algorithm. This is realized with a datapath of two accumulators. The system should be able to use the complete dynamic range of 2^{15} bits (signed) within one interpolating interval. To meet these requirements the input has to be shifted and the internal accuracy of the datapath has to be 40 bits. Simulations of the datapath have shown that although the accumulators uses more resources, the system performance requires only a low cost FPGA like the Altera CycloneII.

