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Mavric, U.

Paper Title Page
WEPMN102 A 96 Channel Receiver for the ILCTA LLRF System at Fermilab 2271
  • U. Mavric, J. Branlard, B. Chase, E. Cullerton, D. W. Klepec
    Fermilab, Batavia, Illinois
  The present configuration of an ILC Main Linac RF station has 26 nine cell cavities driven from one klystron. With the addition of waveguide power coupler monitors, 96 RF signals will be downconverted and processed. A downconverter chassis is being developed that contains 12 eight channel analog modules and a single upconverter module. This chassis will first be deployed for testing a cryomodule composed of eight cavities located at New Muon Laboratory (NML) - Fermilab. Critical parts of the design for LLRF applications are identified and a detailed description of the circuit with various characteristic measurements is presented. The board is composed of an input band-pass filter centered at 1.3GHz, followed by a mixer, which downconverts the cavity probe signal to a proposed 13 MHz intermediate frequency. Cables with 8 channels per connector and good isolation between channels are being used to interconnect each downconverter module with a digital board. As mixers and power splitters are the most sensitive parts for noise, nonlinearities and cross-talk issues, special attention is given to these parts in the design of the LO port multiplication and distribution.  
WEPMN112 Multichannel Vector Field Control Module for LLRF Control of Superconducting Cavities 2298
  • P. Varghese, B. Barnes, J. Branlard, B. Chase, P. W. Joireman, D. W. Klepec, U. Mavric, V. Tupikov
    Fermilab, Batavia, Illinois
  The field control of multiple superconducting RF cavities with a single Klystron, such as the proposed RF scheme for the ILC, requires high density (number of RF channels) signal processing hardware so that vector control may be implemented with minimum group delay. The MFC (Multichannel Field Control) module is a 33-channel, FPGA based downconversion and signal processing board in a single VXI slot, with 4 channels of high speed DAC outputs. An LO input of upto 1.6 GHz can be divided down to provide 8 clock signals through a clock distribution chip. A 32-bit, 400MHz floating point DSP provides additional computational capability for calibration and implementation of more complex control algorithms. Both the FPGA and DSP have external SDRAM memory for diagnostic data and nonvolatile Flash memory for program and configuration storage. Multiple high speed serial transceivers on the front panel and the backplane bus allow a flexible architecture for inter-module real time data exchanges. An interface CPLD supports the VXI bus protocol for communication to a Slot0 CPU, with Ethernet connections for remote in system programming of the FPGA and DSP as well as for data acquisition.  
WEPMN092 Capture Cavity II Results at FNAL 2245
  • J. Branlard, G. I. Cancelo, R. H. Carcagno, B. Chase, H. Edwards, R. P. Fliller, B. M. Hanna, E. R. Harms, A. Hocker, T. W. Koeth, M. J. Kucera, A. Makulski, U. Mavric, M. McGee, A. H. Paytyan, Y. M. Pischalnikov, P. S. Prieto, R. Rechenmacher, J. Reid, K. R. Treptow, N. G. Wilcer, T. J. Zmuda
    Fermilab, Batavia, Illinois
  Funding: FRA

As part of the research and development towards the International Linear Collider (ILC), several test facilities have been developed at Fermilab. This paper presents the latest LLRF results obtained with Capture Cavity II at these test facilities. The main focus will be on controls and RF operations using the SIMCON based LLRF system. Details about hardware upgrades and overall system performance will be also explained. Finally, design considerations and objectives for the future test facility at the New Muon Laboratory (NML) will be presented.