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Grassellino, A.

Paper Title Page
MOPAS086 FPGA Based ILC Cavity Simulator 632
  • A. Grassellino, J. K. Keung, F. M. Newcomer
    University of Pennsylvania, Philadelphia, Pennsylvania
  • N. Lockyer
    TRIUMF, Vancouver
  In the proposed International Linear Collider (ILC) design, the Low Level RF (LLRF) control system plays the important role of maintaining the proper phase and amplitude information for the RF field inside the superconducting cavities. The high operational overhead of the high power cryogenic hardware and the risk of its damage during the control hardware tests make it necessary to have a LLRF test bed independent of the real hardware. Thus, we have developed a Real Time Simulator (RTS), an FPGA based ILC RF unit simulator, which will be useful for the testing and commissioning of the Low Level RF control system, including the exception handling capabilities, and possibly as a noiseless behavioral reference for each cryomodule during operation. The RTS has been implemented on a Lyrtech VHS-ADAC board. It includes effects such as Lorentz Detuning and presently an overall latency lower than 200 nanoseconds has been achieved. The status of the RTS and the conclusions derived from the simulations will be reported, along with LLRF interface tests results.