A   B   C   D   E   F   G   H   I   J   K   L   M   N   O   P   Q   R   S   T   U   V   W   X   Y   Z  

Chin, M. J.

Paper Title Page
MOPAS031 Hardware and Software Development and Integration in an FPGA Embedded Processor Based Control System Module for the ALS 503
 
  • J. M. Weber, M. J. Chin, CA. Timossi, E. C. Williams
    LBNL, Berkeley, California
  
  Funding: This work was supported by the Director, Office of Science, Office of Basic Energy Sciences, of the U. S. Department of Energy under Contract No. DE-AC02-05CH11231.

The emergence of Field Programmable Gate Arrays (FPGAs) with embedded processors and significant progress in their development tools have contributed to the realization of system-on-a-chip networked front-end systems. Embedded processors are capable of running full-fledged Real-Time Operating Systems (RTOSs) and serving channels via Ethernet while high speed hardware functions, such as digital signal processing and high performance interfaces, run simultaneously in the FPGA logic. Despite significant advantages of the system-on-a-chip implementation, engineers have shied away from designing such systems due to the perceived daunting task of integrating software to run a RTOS with custom hardware. However, advances in embedded development tools considerably reduce the effort required for software/hardware integration. This paper will describe the implementation and integration of software and hardware in an FPGA embedded processor system as illustrated by the design of a new control system module for the ALS.

 
TUPMS003 Status of the Top-off Upgrade of the ALS 1197
 
  • C. Steier, B. J. Bailey, K. M. Baptiste, W. Barry, A. Biocca, W. E. Byrne, M. J. Chin, R. J. Donahue, R. M. Duarte, M. P. Fahmie, J. Gath, S. R. Jacobson, J. Julian, J.-Y. Jung, S. Kwiatkowski, S. Marks, R. S. Mueller, H. Nishimura, J. W. ONeill, S. Prestemon, D. Robin, S. L. Rossi, F. Sannibale, T. Scarvie, D. Schlueter, D. Shuman, G. D. Stover, CA. Timossi, T. Warwick, J. M. Weber, E. C. Williams
    LBNL, Berkeley, California
  
  Funding: This work was supported by the Director, Office of Science, Office of Basic Energy Sciences, U. S. Department of Energy under Contract No. DE-AC02-05CH11231.

The Advanced Light Source is currently being upgraded for top-off operation. This major facility upgrade will provide an improvement in brightness from soft x-ray undulators of about one order of magnitude and keep the ALS competitive with the newest intermediate energy light sources. Major components of the upgrade include making the booster synchrotron capable of full energy operation, radiation safety studies, improvements to interlocks and collimation systems, diagnostics upgrades as well as emittance improvements in the main storage ring. The project status will be discussed as well as results of major parts of the commissioning.

 
FRPMS030 ALS Mini IOC: An FPGA Embedded Processor Based Control System Module for Booster Magnet Ramping at the ALS 3991
 
  • J. M. Weber, M. J. Chin, CA. Timossi, E. C. Williams
    LBNL, Berkeley, California
  
  Funding: This work was supported by the Director, Office of Science, Office of Basic Energy Sciences, of the U. S. Department of Energy under Contract No. DE-AC02-05CH11231.

The ALS booster magnet upgrade for top off operation requires new instrumentation to meet increased magnet ramping requirements. To address these requirements, the ALS Instrumentation and Controls groups collaborated to design a new control system module called the Mini IOC. The Mini IOC hardware is based on a commercial evaluation board containing an FPGA with embedded processor and built-in interfaces for 128MB of DDR SDRAM and Ethernet. A custom module is used for analog controls and monitors. The PowerPC embedded processor runs an EPICS database built on the VxWorks operating system allowing remote access via Ethernet. This paper includes an overview of the Mini IOC design and operational results.