Low Level RF (LLRF) control systems of linear accelerators (LINACs) are typically implemented with heterodyne based architectures, which have complex analog RF mixers for up and down conversion. The Gen 3 RF System-on-Chip (RFSoC) device from AMD Xilinx integrates data converters with maximum RF frequency of 6 GHz. That enables direct RF sampling of C-band LLRF signal typically operated at 5.712 GHz without RF mixers, which can significantly simplify the system architecture. The data converters sample RF signals in higher order Nyquist zones and then up or down converted digitally by the integrated data path. The closed-loop feedback control firmware implemented in FPGA integrated in RFSoC can process the baseband signal from the ADC data path and calculate the updated phase and amplitude to be up-mixed by the DAC data path. We have developed an LLRF control RFSoC platform, which targets Cool Copper Collider (C3) and other C or S band LINAC research and development projects. In this paper, the architecture of the platform and the test results for some of the key performance parameters, such as phase and amplitude stability with our custom solid-state amplifier, will be described.

The BEam COoler and LAser spectroscopy (BECOLA) is a collinear laser spectroscopy facility at the Facility for Rare Isotope Beams (FRIB) at Michigan State University. Time resolved laser spectroscopy experiments are performed here to study the nuclear structure of radioactive isotopes. The current data acquisition (DAQ) system being used is based on AMD Spartan 6 field programmable gate array (FPGA) and has a time resolution of 8 ns. There was a need to upgrade existing hardware to meet the requirements for higher time resolution of fast ion detectors. A new DAQ system with AMD Zynq System on Chip (SoC) FPGA based time-resolved scaler was designed, developed and fabricated. It achieves a time resolution of 2 ns. The current amplifier-discriminator has an output pulse resolution of 10 ns. To address this constraint and fully leverage the 2 ns time resolution provided by the new SoC FPGA, a new AD with an output pulse resolution of 1 ns was designed. A brief overview of the upgraded DAQ system will be discussed in this paper, including its features, improvements and future updates.

The LHC Abort Gap Monitor (AGM) is part of the LHC machine protection system (MPS) and is designed to measure the particle population in a 3us wide region known as the "abort gap." This region needs to be kept empty to ensure safe beam dumps. The AGM captures the synchrotron light generated in the visible part of the spectra and converts it into an electric signal. This signal is then processed by an acquisition system and can trigger the ‘abort gap cleaning’ process. The current AGM, which has been in operation since 2010, uses an analogue integrator ASIC and a 40 MHz analogue-to-digital (ADC) converter to provide the particle population information. However, this solution is now considered obsolete and is being replaced by a digital signal processing approach. Working directly in the digital domain not only offers more scalability but also better determinism and reliability. This work presents the new technical solution for the acquisition chain, compares the characteristics of both implementations, and showcases recent measurements conducted on the LHC ion beams.

Paul Scherrer Institute (PSI) has led significant advancements in accelerator electronics development, leveraging Field Programmable Gate Arrays (FPGA) based Digital Signal Processing (DSP) across various critical systems, including Low Level RF (LLRF), Longitudinal Beam Loss Monitoring (LBLM), charge particle measurement via Integrating Current Transformers (ICT), Timing, Filling Pattern Monitor (FPM), Beam Position Monitor (BPM) and other essential beam instruments. Over the past decade, PSI’s approach to develop in-house control system platform (e.g. CPCI-S.0), has encouraged innovation. The strategic reorganization within PSI, fostering collaboration among FPGA firmware engineers, led to the inception of Open-Source FPGA DSP libraries hosted on GitHub. Serving as a comprehensive repository, these libraries empower developers by providing common FPGA IPs, fundamental DSP algorithms and Fixed-Point (FP) arithmetic units. Their presence advances prototype development by enabling rapid assembly of several measurement and or control concepts. In this contribution, we present the features and the transformative impact of the PSI Open-source FPGA libraries with a focus on LLRF. This initiative has not only empowered our team to provide valuable insights, but has also streamlined the integration of new recruits and students, enabling the seamless continuation of FPGA design frameworks.

The Radio Frequency System-on-Chip (RFSoC) FPGA-based high-performance bunch-by-bunch beam position monitor (BxB BPM) was developed and commissioned at NSLS-II. The new BxB BPM features a 14-bit 5 Gsps ADC, directly sampling 2 ns four-button signals, and digital signal processing with a synchronized 500 MHz RF reference clock. The BxB BPM provides 32 K points of ADC raw data, 5 K turns for up to 1320 bunch amplitude and position data, 2.6 million turn-by-turn (TxT) data points, 10 K turns of circular buffer, and 10 Hz streaming data. The potential applications include, but are not limited to measuring injection transient, efficiency, ion instability detection, and single/multi-bunch motion analysis. A ~15 μm single-bunch resolution was confirmed with the beam test. This paper will present the beam test results, hardware FPGA firmware architecture, and control system interface for operation.

BPM signal processing uses digital or analog down-conversion to report phase and magnitude at a single frequency, however the digitized BPM signal may contain many more harmonics and a larger bandwidth of information which may be useful. An FPGA implementation is described which captures the full bandwidth BPM signal with minimal processing and resources. This approach can be scaled to captures as many beam harmonics as needed, limited only by the bandwidth of the ADC used. The periodic nature of the BPM signal is utilized to use time-interleaved sampling to effectively multiply the sampling rate of the ADC.

Ultrafast high repetition-rate laser systems are essential to modern scientific and industrial applications. Variations in critical figures of merit, such as focal position, can significantly impact efficacy for applications involving laser plasma interactions, such as electron beam acceleration and radiation generation. We present a diagnostic and correction scheme for controlling and determining laser focal position by utilizing fast wavefront sensor measurements from multiple positions to train a focal position predictor. We present the deployment and testing of this scheme at the BELLA Center at Lawrence Berkeley National Laboratory. Online optical adjustments are made to a telescopic lens to provide the desired correction on millisecond timescales. A framework for generating a low-level hardware description of ML-based correction algorithms on FPGA hardware is coupled directly to the beamline using the AMD Xilinx Vitis AI toolchain in conjunction with deployment scripts.

In FRIB we use chopper in the low energy beam line for beam power controls. As appropriate functioning of chopper is critical for both beam operation and machine protection, an FPGA-based chopper monitoring system was developed to monitor its operation for fixed duty cycle operation and has been in use to support operation. The chopper monitor shuts off beam promptly at detection of a deviation of duty cycle outside tolerance. For future higher beam power operation, automatic beam power ramp modes will be required where beam duty factor is dynamically ramped up following a predetermined sequence. Recently FPGA prototype is developed to enhance the chopper monitor to accommodate one of such dynamic modes, cold start beam mode. It is a design challenge to integrate all the beam modes in one FPGA while synchronizing with external timing system pulse generator and recording the process data and failure information. Detailed FPGA design for this enhancement of chopper monitor will be discussed in this paper, followed by the test result of integrated system of chopper monitor, global timing system pulse generator, high voltage switch of chopper control and EPICS control software.

Located in Saskatoon, Saskatchewan, Canada, the Canadian Light Source (CLS) has been operation since 2003. CLS is a 3rd generation Synchrotron Light Source operating at 2.9GeV. The CLS Booster RF system uses a 100 kW, 500 MHz solid-state power amplifier to power two 5-cell “PETRA” cavities. Recently ALBA and CLS collaborated to commission a CLS-constructed version of the ALBA Digital Low-Level RF system in the CLS Booster ring RF system to replace the aging analog low-level RF system. Changes were required to address differing configuration and requirements between the CLS and ALBA RF systems. Challenges and opportunities for system machine safety, reliability, and performance improvements identified during and after commissioning have been addressed. Hardware configuration changes were implemented. Additional hardware devices have been produced and incorporated to streamline interfacing and to mitigate some risks.

Nowadays, the real-time control is more and more popular in the particle accelerator field because it is a powerful tool for stable operation and beam loss suppression in the particle accelerator. However, in the Japan Proton Accelerator Research Complex (J-PARC) Main Ring (MR), real-time control has not been widely used in magnet power supplies yet. Magnet power supplies are very easily affected by disturbances from external factors, such as environmental temperature, device aging, power grid voltage and current fluctuations, and so on. Therefore, it is worth developing a real-time digital controller with general functions for the magnet power supplies to observe and suppress these disturbances. In this paper, we propose the design of a general-purpose intelligence controller for the magnet power supply realized by a System-on-Chip (SoC) Field Programmable Gate Array (FPGA). This digital controller can also be used as a high-resolution data acquisition system, a pattern generator, and a high-precision current control system for magnet power supplies.