The Future Circular Electron-Positron Collider (FCC-ee) is CERN's leading proposal for the next generation of energy-frontier particle accelerators. To reach integrated luminosity goals, it aims to be operational for minimum 80 % of the scheduled 185 physics days each year. For comparison, the Large Hadron Collider (LHC) achieved 77 % in 2016-2018. There are additional challenges in the FCC-ee due to its size, complexity and ambitious technical objectives. Availability is therefore a significant risk to physics deliverables. This paper presents the framework used to analyse availability and luminosity in the FCC-ee. To showcase its capabilities, first, a top-level system deconstruction reveals several key relationships for the Radio Frequency (RF) system. Second, two proposed technologies are simulated to overcome constraints in the Z, W operation cycle. Of these, pre-polarised bunch injection (PPBI) shows tremendous advantage for shielding integrated luminosity from a challenging availability environment.

The Beam Interlock System (BIS) is the backbone of the machine protection system throughout the accelerator complex at CERN, from LINAC4 to the LHC. After 15 years of flawless operation, a new version of the BIS is currently being produced and will be installed in the LHC, SPS and North Area during CERN’s Long Shutdown 3, planned to start in 2026. Overall, more than 3,000 Printed Circuit Boards will be produced and assembled outside CERN. In addition, more than 120,000 lines of firmware and supporting scripts are written to implement the critical and monitoring functionalities of the BIS. Both hardware and firmware need to be thoroughly tested before installation and operation to guarantee the high levels of reliability and availability required by the operation of the accelerators. In this paper we present the testing methodology including the development of dedicated testbeds for hardware validation, the use of comprehensive simulation and continuous integration for firmware development, and the implementation of automated tests for system-level functional validation.

The Safe Machine Parameter (SMP) system is an electronic hardware-based system which has been an integral part of the LHC’s machine protection strategy since it started operation. Its primary objective is to provide several parameters and interlock signals to critical machine protection users across the LHC and SPS accelerators, whilst prioritizing high reliability and availability. After almost two decades of operation, there is a need to upgrade the SMP hardware electronics. In the High Luminosity LHC era the requirements of connected systems have changed, leading to new system functions and operational requirements which must be integrated into the new design. This paper details the electronic design considerations of developing the second-generation SMP. The general distribution of parameters relies on the CERN WhiteRabbit timing network renovation, for which dedicated high-precision clock components were selected and tested on a prototype board. Details of the hardware design and validation are discussed, along with the comprehensive upgrades aimed at delivering an SMP system with expanded monitoring and diagnostic features.