The LHC interlock BPM system is used as part of the beam abort system to insure that beam trajectories in those regions are conform with a safe extraction of the beams from the main ring to the dump lines. After more than 10 years of operation, the system has shown some limitations in bandwidth and dynamic range and a study was initiated to look for improvements. Nowadays, with the availability of multi giga sample per second sampling rate ADC converters, there is poten-tial to greatly improve the performance of the system. In this paper a wideband architecture with direct acqui-sition of the BPM electrode signals, time interleaved on the same read-out channel is presented with emphasis on the design and construction of the critical components, and on the measured performance of a prototype system tested in the LHC during the 2022 run.