IHEP, Beijing, People’s Republic of China
High Energy Photon Source (HEPS) is a 6 GeV diffraction-limited synchrotron light source currently under construction in Beijing. It adopts a double-frequency RF system with 166.6 MHz as fundamental and 499.8 MHz as third harmonic. The fundamental cavity is making use of a superconducting quarter-wave β=1 structure and the third harmonic is of superconducting elliptical single-cell geometry for the storage ring, while normal-conducting 5-cell cavities are chosen for the booster ring. A total of 900 kW RF power shall be delivered to the beam by the 166.6 MHz cavities and the third harmonic cavities are active. All cavities are driven by solid-state power amplifiers and the RF fields are regulated by digital low-level RF control systems. The cavity and ancillaries, high-power RF system and low-level RF control system are in the prototyping phase. This paper presents the current status and progress of the RF system for HEPS.
IHEP, Beijing, People’s Republic of China
A new interlock and data acquisition (DAQ) system is being developed for the RF system at High Energy Photon Source (HEPS) to protect essential devices as well as to locate the fault. Various signals collected and pre-processed by the DAQ system and individual interlock signals from solid-state power amplifiers, low-level RFs, arc detectors, etc. are sent to the interlock system for logic decision to control the RF switch. Programmable logic controllers (PLC) are used to collect slow signals like temperature, water flowrate, etc., while fast acquisition for RF signals is realized by dedicated boards with down-conversion frontend and digital signal processing boards. In order to improve the response time, field programmable gate array (FPGA) has been used for interlock logic implementation with an embedded experimental physics and industrial control system (EPICS). Data storage is managed by using EPICS Archiver Appliance and an operator interface is developed by using Control System Studio (CSS) running on a standalone computer. This paper presents the design and the first test of the new interlock and DAQ for HEPS RF system.
