IPAC2018 - List of Authors (Yan, Y.B.)

Paper	Title	Page
THPML069	The Control System Design of SCLF	4800
	Y.B. Yan, J.G. Ding, G.Y. Jiang, Y.B. Leng SSRF, Shanghai, People's Republic of China J.F. Chen SINAP, Shanghai, People's Republic of China
	The high-gain free electron lasers have given scientists hopes for new scientific discoveries in many frontier research areas. The Shanghai Coherent Light Facility (SCLF) was proposed by the central government of China on April 2017, which is a quasi-continuous wave hard X-ray free electron laser facility. The control system is responsible for the facility-wide device control, data acquisition, machine protection, high level database or application, as well as network and computing platform. It will be mainly based on EPICS to reach the balance between the high performance and costs of maintenance. The latest technology will be adopted for the high repetition rate data acquisition and feedback system. The details of the control system design will be reported in this paper.
DOI •	reference for this paper ※ https://doi.org/10.18429/JACoW-IPAC2018-THPML069
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THPML071	Upgrade of Digital BPM Processor at DCLS and SXFEL	4807
	L.W. Lai, F.Z. Chen, Y.B. Leng, T. Wu, Y.B. Yan SSRF, Shanghai, People's Republic of China J. Chen SINAP, Shanghai, People's Republic of China
	A digital BPM processor has been developed at 2016 in SINAP for DCLS and SXFEL, which are FEL facilities built in China. The stripline BPM and cavity BPM processors share the same hardware platform and firmware, but the processing algorithms implemented in EPICS IOC on the ARM CPU are different. The capability of the ARM limits the processing speed to 10 bunches per second. Now the bunch rate of DCLS and SXFEL are going to increase from 10Hz to 50Hz. To meet the higher processing speed requirements, the processor firmware and software are upgraded in 2017. All BPM signal processing algorithms are implemented in FPGA, and EPICS IOC reads results only. After the upgrade, the processing speed reach 120 bunches per second. And this is also a good preparation for future Shanghai Hard-X ray FEL, which bunch rate is about 1MHz.
DOI •	reference for this paper ※ https://doi.org/10.18429/JACoW-IPAC2018-THPML071
Export •	reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

Paper

Title

Page

The Control System Design of SCLF

4800

Y.B. Yan, J.G. Ding, G.Y. Jiang, Y.B. Leng
SSRF, Shanghai, People's Republic of China
J.F. Chen
SINAP, Shanghai, People's Republic of China

The high-gain free electron lasers have given scientists hopes for new scientific discoveries in many frontier research areas. The Shanghai Coherent Light Facility (SCLF) was proposed by the central government of China on April 2017, which is a quasi-continuous wave hard X-ray free electron laser facility. The control system is responsible for the facility-wide device control, data acquisition, machine protection, high level database or application, as well as network and computing platform. It will be mainly based on EPICS to reach the balance between the high performance and costs of maintenance. The latest technology will be adopted for the high repetition rate data acquisition and feedback system. The details of the control system design will be reported in this paper.

DOI •

reference for this paper ※ https://doi.org/10.18429/JACoW-IPAC2018-THPML069

Export •

reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

THPML071

Upgrade of Digital BPM Processor at DCLS and SXFEL

4807

L.W. Lai, F.Z. Chen, Y.B. Leng, T. Wu, Y.B. Yan
SSRF, Shanghai, People's Republic of China
J. Chen
SINAP, Shanghai, People's Republic of China

A digital BPM processor has been developed at 2016 in SINAP for DCLS and SXFEL, which are FEL facilities built in China. The stripline BPM and cavity BPM processors share the same hardware platform and firmware, but the processing algorithms implemented in EPICS IOC on the ARM CPU are different. The capability of the ARM limits the processing speed to 10 bunches per second. Now the bunch rate of DCLS and SXFEL are going to increase from 10Hz to 50Hz. To meet the higher processing speed requirements, the processor firmware and software are upgraded in 2017. All BPM signal processing algorithms are implemented in FPGA, and EPICS IOC reads results only. After the upgrade, the processing speed reach 120 bunches per second. And this is also a good preparation for future Shanghai Hard-X ray FEL, which bunch rate is about 1MHz.

DOI •

reference for this paper ※ https://doi.org/10.18429/JACoW-IPAC2018-THPML071

Export •

reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)