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TY - CONF AU - Duan, Q.M. AU - Yang, Y.L. ED - Schaa, Volker RW ED - Arduini, Gianluigi ED - Pranke, Juliana ED - Seidel, Mike ED - Lindroos, Mats TI - The Development of Tune Measurement System Based on FPGA at HLSII Storage Ring J2 - Proc. of IPAC2017, Copenhagen, Denmark, 14â19 May, 2017 C1 - Copenhagen, Denmark T2 - International Particle Accelerator Conference T3 - 8 LA - english AB - A tune measurement system based on FPGA development board is developed at HLS II. The FPGA development board based on Zynq SOC, have ADC and DAC on board. The FPGA can provide two kinds of signal for exciting the beam: parametric frequency sweep signal and bandwidth limited white noise signal. The FFT algorithms and calculation of tune are running in the ARM CPU. In order to compare performance with the original system which is based on spectrum analyzer, we did experiments with new system based FPGA and original system respectively. The experiments on HLSII storage ring show that the tune measuring accuracy have reached 0.0006 / 0.0001 in horizontal and vertical direction based on sweep frequency of FPGA-based system. PB - JACoW CP - Geneva, Switzerland SP - 305 EP - 308 KW - FPGA KW - storage-ring KW - experiment KW - status KW - synchrotron DA - 2017/05 PY - 2017 SN - 978-3-95450-182-3 DO - 10.18429/JACoW-IPAC2017-MOPAB080 UR - http://jacow.org/ipac2017/papers/mopab080.pdf ER -