IPAC2016 - List of Authors (Kwon, S.J.)

Paper	Title	Page
THPMW012	The Fast Interlock Controller for High Power Pulse Modulator at PAL-XFEL	3561
	S.H. Kim, H.-S. Kang, K.H. Kim, S.J. Kwon, H.-S. Lee, S.S. Park, Y.J. Park PAL, Pohang, Kyungbuk, Republic of Korea I.S. Ko POSTECH, Pohang, Kyungbuk, Republic of Korea
	Funding: This work is supported by Ministry of Science, ICT(Information/Communication Technology) and Future Planning. The modulator control system for PAL-XFEL consists of a PLC unit (Programmable Logic Controller) and FPSCM (Fast Pulse Signal Conditioning Module). There are two kinds of interlock, which are dynamic and static interlocks categorized as analogue monitor and control signals, digital monitor and control signals. In case of dynamic interlocks, the internal interface of the PLC unit had to be modified due to operating within 10 ms time response from the interlock event. The fast pulse signal conditioning module is adopted for preconditioning the fast pulse and DC signals that inherently have high noise levels generated from a beam voltage, a beam current and EOLC current. Those EM (Electro-Magnetic) noises are generated by thyratron switching. The amplitude of the thyratron noise is large which causes the problem at the control devices, frequently. In this paper, the test results of the interlock control system will be described.
DOI •	reference for this paper ※ DOI:10.18429/JACoW-IPAC2016-THPMW012
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Paper

Title

Page

The Fast Interlock Controller for High Power Pulse Modulator at PAL-XFEL

3561

S.H. Kim, H.-S. Kang, K.H. Kim, S.J. Kwon, H.-S. Lee, S.S. Park, Y.J. Park
PAL, Pohang, Kyungbuk, Republic of Korea
I.S. Ko
POSTECH, Pohang, Kyungbuk, Republic of Korea

Funding: This work is supported by Ministry of Science, ICT(Information/Communication Technology) and Future Planning.
The modulator control system for PAL-XFEL consists of a PLC unit (Programmable Logic Controller) and FPSCM (Fast Pulse Signal Conditioning Module). There are two kinds of interlock, which are dynamic and static interlocks categorized as analogue monitor and control signals, digital monitor and control signals. In case of dynamic interlocks, the internal interface of the PLC unit had to be modified due to operating within 10 ms time response from the interlock event. The fast pulse signal conditioning module is adopted for preconditioning the fast pulse and DC signals that inherently have high noise levels generated from a beam voltage, a beam current and EOLC current. Those EM (Electro-Magnetic) noises are generated by thyratron switching. The amplitude of the thyratron noise is large which causes the problem at the control devices, frequently. In this paper, the test results of the interlock control system will be described.

DOI •

reference for this paper ※ DOI:10.18429/JACoW-IPAC2016-THPMW012

Export •

reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)