THBR04
University of Pittsburgh, Pittsburgh, Pennsylvania, USA
We present a novel implementation of classification using boosted decision trees (BDT) on FPGA. Our BDT approach offers an alternative to existing packages, including those that implement neural networks on FPGA, with less dependence of DSP utilization that is replaced by other resources. Our design philosophy is to remove clocked operations in favor of combinatoric logic through High Level Synthesis. The firmware implementation of binary classification requiring 100 training trees with a maximum depth of 4 using four input variables gives a latency value of about 10ns at various clock speeds. We optimize the parameters using a software package, which interfaces to Xilinx Vivado through High Level Synthesis. Such a tool may enable the FPGA-based trigger systems at the Large Hadron Collider to be more sensitive to new physics at high energy experiments. The work is described in https://arxiv.org/abs/2104.03408
