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@InProceedings{moudden:icalepcs2019-wepha103,
author = {Y. Moudden and A. Barbuti and G. Caulier and T. Poirier and B. Santraine and B. Vincent},
title = {{Backward Compatible Update of the Timing System of WEST}},
booktitle = {Proc. ICALEPCS'19},
pages = {1338--1342},
paper = {WEPHA103},
language = {english},
keywords = {FPGA, network, timing, distributed, controls},
venue = {New York, NY, USA},
series = {International Conference on Accelerator and Large Experimental Physics Control Systems},
number = {17},
publisher = {JACoW Publishing, Geneva, Switzerland},
month = {08},
year = {2020},
issn = {2226-0358},
isbn = {978-3-95450-209-7},
doi = {10.18429/JACoW-ICALEPCS2019-WEPHA103},
url = {https://jacow.org/icalepcs2019/papers/wepha103.pdf},
note = {https://doi.org/10.18429/JACoW-ICALEPCS2019-WEPHA103},
abstract = {Between 2013 and 2016, the tokamak Tore Supra in operation at Cadarache (CEA-France) since 1988 underwent a major upgrade following which it was renamed WEST (Tungsten [W] Environment in Steady state Tokamak). The synchronization system however was not upgraded since 1999*. At the time, a robust design was achieved based on AMD’s TAXI chip**: clock and events are distributed from a central emitter over a star shaped network of simplex optical links to electronic crates around the tokamak. Unfortunately, spare boards were not produced in sufficient quantities and the TAXI is obsolete. In fact, multigigabit serial communication standards question the future availability of any such low rate SerDeses. Designing replacement boards provides an opportunity for a new CDR solution and extended functionalities (loss-of-lock detection, latency monitoring). Backward compatibility is a major constraint given the lack of resources for a full upgrade. We will first describe the current state of the timing network of WEST, then the implementation of a custom CDR in full firmware, using the IOSerDeses of Xilinx FPGAs and will finally provide preliminary results on development boards.},
}