ICALEPCS2011 - List of Authors (Baer, R.)

Paper

Title

Page

Performance Tests of the Standard FAIR Equipment Controller Prototype

919

S. Rauch, R. Bär, W. Panschow, M. Thieme
GSI, Darmstadt, Germany

For the control system of the new FAIR accelerator facility a standard equipment controller, the Scalable Control Unit (SCU), is presently under development. First prototypes have already been tested in real applications. The controller combines an x86 ComExpress Board and an Altera Arria II FPGA. Over a parallel bus interface called the SCU bus, up to 12 slave boards can be controlled. Communication between CPU and FPGA is done by a PCIe link. We discuss the real time behaviour between the Linux OS and the FPGA Hardware. For the test, a Front-End Software Architecture (FESA) class, running under Linux, communicates with the PCIe bridge in the FPGA. Although we are using PCIe only for single 32 bit wide accesses to the FPGA address space, the performance still seems sufficient. The tests showed an average response time to IRQs of 50 microseconds with a 1.6 GHz Intel Atom CPU. This includes the context change to the FESA userspace application and the reply back to the FPGA. Further topics are the bandwidth of the PCIe link for single/burst transfers and the performance of the SCU bus communication.

WEPMS011

The Timing Master for the FAIR Accelerator Facility

996

R. Bär, T. Fleck, M. Kreider, S. Mauro
GSI, Darmstadt, Germany

One central design feature of the FAIR accelerator complex is a high level of parallel beam operation, imposing ambitious demands on the timing and management of accelerator cycles. Several linear accelerators, synchrotrons, storage rings and beam lines have to be controlled and re-configured for each beam production chain on a pulse-to-pulse basis, with cycle lengths ranging from 20 ms to several hours. This implies initialization, synchronization of equipment on the time scale down to the ns level, interdependencies, multiple paths and contingency actions like emergency beam dump scenarios. The FAIR timing system will be based on White Rabbit [1] network technology, implementing a central Timing Master (TM) unit to orchestrate all machines. The TM is subdivided into separate functional blocks: the Clock Master, which deals with time and clock sources and their distribution over WR, the Management Master, which administrates all WR timing receivers, and the Data Master, which schedules and coordinates machine instructions and broadcasts them over the WR network. The TM triggers equipment actions based on the transmitted execution time. Since latencies in the low μs range are required, this paper investigates the possibilities of parallelisation in programmable hardware and discusses the benefits to either a distributed or monolithic timing master architecture. The proposed FPGA based TM will meet said timing requirements while providing fast reaction to interlocks and internal events and offers parallel processing of multiple signals and state machines.
[1] J. Serrano, et al, "The White Rabbit Project", ICALEPCS 2009.

FRCAUST01

The Control System for the FAIR facility – Project Status and Design Overview

R. Bär
GSI, Darmstadt, Germany

In the next few years the international accelerator complex FAIR (Facility for Anti-protons and Ion Research) will be erected at GSI, substantially extending the present GSI accelerators then being used as injectors. FAIR will provide anti-proton, ion, and rare isotope beams with unprecedented intensity and quality. For FAIR, a new accelerator control system is presently under development that addresses all aspects of the functionality to operate the GSI/FAIR machines and moreover integrates the present GSI control system infrastructure. One prominent challenge is the complex operation scheme with the handling and management of massive parallel beam operation which imposes ambitious demands on the timing and cycle management system. This presentation shortly summarizes the general status of the FAIR project and major challenges following from being an international project. We focus on the progress of the general control system design, system architecture, technology validation and choices, and integration of complete controls building blocks developed or adapted in the framework of collaborations. The presentation is supplemented by reporting our activities of retrofitting the present GSI control system stack to allow integration into the new FAIR controls environment.

Slides FRCAUST01 [1.698 MB]

Paper	Title	Page
WEPMN018	Performance Tests of the Standard FAIR Equipment Controller Prototype	919
	S. Rauch, R. Bär, W. Panschow, M. Thieme GSI, Darmstadt, Germany
	For the control system of the new FAIR accelerator facility a standard equipment controller, the Scalable Control Unit (SCU), is presently under development. First prototypes have already been tested in real applications. The controller combines an x86 ComExpress Board and an Altera Arria II FPGA. Over a parallel bus interface called the SCU bus, up to 12 slave boards can be controlled. Communication between CPU and FPGA is done by a PCIe link. We discuss the real time behaviour between the Linux OS and the FPGA Hardware. For the test, a Front-End Software Architecture (FESA) class, running under Linux, communicates with the PCIe bridge in the FPGA. Although we are using PCIe only for single 32 bit wide accesses to the FPGA address space, the performance still seems sufficient. The tests showed an average response time to IRQs of 50 microseconds with a 1.6 GHz Intel Atom CPU. This includes the context change to the FESA userspace application and the reply back to the FPGA. Further topics are the bandwidth of the PCIe link for single/burst transfers and the performance of the SCU bus communication.

WEPMS011	The Timing Master for the FAIR Accelerator Facility	996
	R. Bär, T. Fleck, M. Kreider, S. Mauro GSI, Darmstadt, Germany
	One central design feature of the FAIR accelerator complex is a high level of parallel beam operation, imposing ambitious demands on the timing and management of accelerator cycles. Several linear accelerators, synchrotrons, storage rings and beam lines have to be controlled and re-configured for each beam production chain on a pulse-to-pulse basis, with cycle lengths ranging from 20 ms to several hours. This implies initialization, synchronization of equipment on the time scale down to the ns level, interdependencies, multiple paths and contingency actions like emergency beam dump scenarios. The FAIR timing system will be based on White Rabbit [1] network technology, implementing a central Timing Master (TM) unit to orchestrate all machines. The TM is subdivided into separate functional blocks: the Clock Master, which deals with time and clock sources and their distribution over WR, the Management Master, which administrates all WR timing receivers, and the Data Master, which schedules and coordinates machine instructions and broadcasts them over the WR network. The TM triggers equipment actions based on the transmitted execution time. Since latencies in the low μs range are required, this paper investigates the possibilities of parallelisation in programmable hardware and discusses the benefits to either a distributed or monolithic timing master architecture. The proposed FPGA based TM will meet said timing requirements while providing fast reaction to interlocks and internal events and offers parallel processing of multiple signals and state machines. [1] J. Serrano, et al, "The White Rabbit Project", ICALEPCS 2009.

FRCAUST01	The Control System for the FAIR facility – Project Status and Design Overview
	R. Bär GSI, Darmstadt, Germany
	In the next few years the international accelerator complex FAIR (Facility for Anti-protons and Ion Research) will be erected at GSI, substantially extending the present GSI accelerators then being used as injectors. FAIR will provide anti-proton, ion, and rare isotope beams with unprecedented intensity and quality. For FAIR, a new accelerator control system is presently under development that addresses all aspects of the functionality to operate the GSI/FAIR machines and moreover integrates the present GSI control system infrastructure. One prominent challenge is the complex operation scheme with the handling and management of massive parallel beam operation which imposes ambitious demands on the timing and cycle management system. This presentation shortly summarizes the general status of the FAIR project and major challenges following from being an international project. We focus on the progress of the general control system design, system architecture, technology validation and choices, and integration of complete controls building blocks developed or adapted in the framework of collaborations. The presentation is supplemented by reporting our activities of retrofitting the present GSI control system stack to allow integration into the new FAIR controls environment.
	Slides FRCAUST01 [1.698 MB]