JACoW is a publisher in Geneva, Switzerland that publishes the proceedings of accelerator conferences held around the world by an international collaboration of editors.
@inproceedings{michnoff:ibic2023-we2c03,
author = {R.J. Michnoff and L. DeSanto and C.M. Degen and D.M. Gassner and S.H. Hafeez and R.L. Hulsart and J.P. Jamilkowski and J. Mead and K. Mernick and G. Narayan and P. Oddo and M.C. Paniccia and J.A. Pomaro and A.C. Pramberger and J.C. Renta and F. Severino},
% author = {R.J. Michnoff and L. DeSanto and C.M. Degen and D.M. Gassner and S.H. Hafeez and R.L. Hulsart and others},
% author = {R.J. Michnoff and others},
title = {{Beam Instrumentation Hardware Architecture for Upgrades at the BNL Collider-Accelerator Complex and the Future Electron Ion Collider}},
% booktitle = {Proc. IBIC'23},
booktitle = {Proc. 12th Int. Beam Instrum. Conf. (IBIC'23)},
eventdate = {2023-09-10/2023-09-14},
pages = {308--311},
paper = {WE2C03},
language = {english},
keywords = {instrumentation, electron, collider, hardware, power-supply},
venue = {Saskatoon, Canada},
series = {International Beam Instrumentation Conference},
number = {12},
publisher = {JACoW Publishing, Geneva, Switzerland},
month = {12},
year = {2023},
issn = {2673-5350},
isbn = {978-3-95450-236-3},
doi = {10.18429/JACoW-IBIC2023-WE2C03},
url = {https://jacow.org/ibic2023/papers/we2c03.pdf},
abstract = {{Many beam instrumentation systems at Brookhaven National Laboratory¿s Collider-Accelerator complex are over 20 years old and in need of upgrading due to obsolete components, old technology and the desire to provide improved performance and enhanced capabilities. In addition, many new beam instrumentation systems will be developed for the future Electron Ion Collider (EIC) that will be housed in the existing Relativistic Heavy Ion Collider (RHIC) tunnel. A new BNL designed custom hardware architecture is planned for both upgrades in the existing facility and new systems for the EIC. A general-purpose carrier board based on the Xilinx Zynq Ultrascale⁺ System-on-Chip (SoC) will interface with a family of application specific daughter cards to satisfy the requirements for each system. This paper will present the general architecture that is planned, as well as details for some of the application specific daughter cards that will be developed.}},
}