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RIS citation export for WEPP27: High Speed Parallel Digital Signal Processing Structure in Bunch-By-Bunch Position Measurement Based on FPGA

TY  - CONF
AU  - Wu, R.Z.
AU  - Lu, P.
AU  - Sun, B.G.
AU  - Tang, L.L.
ED  - Kim, Changbum
ED  - Schaa, Volker R. W.
ED  - Kim, Dong-Eon
ED  - Lee, Jaeyu
TI  - High Speed Parallel Digital Signal Processing Structure in Bunch-By-Bunch Position Measurement Based on FPGA
J2  - Proc. of IBIC2021, Pohang, Rep. of Korea, 24-28 May 2021
CY  - Pohang, Rep. of Korea
T2  - International Beam Instrumentation Conference
T3  - 10
LA  - english
AB  - In storage ring, the measurement of bunch-by-bunch positions can help to obtain abundant beam dynamics characteristic information, diagnose the instability of beam motion and provide a basis for the suppression of instability. However, the measurement of bunch-by-bunch requires one analog-to-digital converter (ADC) with high sampling rate and one processor with fast digital signal processing (DSP)ability. With the development of electronics, high sampling rate ADCs are no longer a problem. Therefore, high-speed DSP has become the key. In this paper, a parallel digital signal processing architecture based on polyphase decomposition is proposed. This architecture realizes the GHz DSP speed on the programmable gate array (FPGA), which can be used as the infrastructure of high-speed DSP in the bunch-by-bunch position measurement system.
PB  - JACoW Publishing
CP  - Geneva, Switzerland
SP  - 434
EP  - 437
KW  - FPGA
KW  - storage-ring
KW  - timing
KW  - synchrotron
KW  - hardware
DA  - 2021/10
PY  - 2021
SN  - 2673-5350
SN  - 978-3-95450-230-1
DO  - doi:10.18429/JACoW-IBIC2021-WEPP27
UR  - https://jacow.org/ibic2021/papers/wepp27.pdf
ER  -