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@inproceedings{wu:ibic2021-wepp27,
author = {R.Z. Wu and P. Lu and B.G. Sun and L.L. Tang},
title = {{High Speed Parallel Digital Signal Processing Structure in Bunch-By-Bunch Position Measurement Based on FPGA}},
booktitle = {Proc. IBIC'21},
pages = {434--437},
eid = {WEPP27},
language = {english},
keywords = {FPGA, storage-ring, timing, synchrotron, hardware},
venue = {Pohang, Rep. of Korea},
series = {International Beam Instrumentation Conference},
number = {10},
publisher = {JACoW Publishing, Geneva, Switzerland},
month = {10},
year = {2021},
issn = {2673-5350},
isbn = {978-3-95450-230-1},
doi = {10.18429/JACoW-IBIC2021-WEPP27},
url = {https://jacow.org/ibic2021/papers/wepp27.pdf},
note = {https://doi.org/10.18429/JACoW-IBIC2021-WEPP27},
abstract = {{In storage ring, the measurement of bunch-by-bunch positions can help to obtain abundant beam dynamics characteristic information, diagnose the instability of beam motion and provide a basis for the suppression of instability. However, the measurement of bunch-by-bunch requires one analog-to-digital converter (ADC) with high sampling rate and one processor with fast digital signal processing (DSP)ability. With the development of electronics, high sampling rate ADCs are no longer a problem. Therefore, high-speed DSP has become the key. In this paper, a parallel digital signal processing architecture based on polyphase decomposition is proposed. This architecture realizes the GHz DSP speed on the programmable gate array (FPGA), which can be used as the infrastructure of high-speed DSP in the bunch-by-bunch position measurement system.}},
}