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Lemut, P. L.

Paper Title Page
TUPC084 Combating Multi-bunch Instabilities with the Libera Bunch-by-bunch Unit 1251
 
  • V. Poucki, T. Karcnik, P. L. Lemut, M. O. Oblak
    Instrumentation Technologies, Solkan
 
  Libera Bunch by Bunch is the digital processing unit for a bunch by bunch feedback system. The upgraded unit has a DSP core application featuring a 16 tap filter for each bunch. DSP processing is organized in 4 chains, following the HW implementation of A/D conversion. Besides setting of FIR filter coefficients in each processing chain, one bunch per chain can have different FIR filter coefficients and provides an option for 4 single bunch processing. All FIR filter coefficients are double buffered. Delays maximally equal to a revolution period are implemented before and after the FIR block. As an additional feature, a phase shift block is introduced that precisely shifts the phase of the output signal in the vicinity of a determined frequency. The core application is accompanied with a Matlab GUI, with an additional window for data acquisition. This system accompanied by a Front End unit provides a complete solution for combating multi bunch beam instabilities. A detailed description and results are presented.  
THPC148 Interlock – the Machine Protection Function of Libera Brilliance 3336
 
  • P. L. Lemut, T. Karcnik, A. Kosicek
    Instrumentation Technologies, Solkan
 
  The basic task of Libera Brilliance is electron beam position measurement. A secondary, but no less important, task is machine protection. Libera Brilliance activates Interlock output when the beam position is outside predefined limits. The Interlock subsystem also activates when the analog-to-digital converters (AD) are saturated and the beam position is only virtually centered. AD converter saturation is detected in the multiplexed fast peak detectors using AD converter rate data. The Interlock is designed for fail-safe operation. Within the FPGA window, a comparator function is performed on the Fast Acquisition position data delivered at a 10 kHz rate. Comparison is done separately for X and Y positions. Limits and operation mode are settable through the CSPI library. To avoid manual resetting of the Interlock, logic output is designed as a monostable cell. The described circuitry has been successfully implemented and tested in both laboratory and accelerator environments.