| Paper | Title | Page |
|---|---|---|
| TUPC048 | Application of a 5 GSPS Analogue Ring Sampling Chip for Low-cost Single-shot BPM Systems | 1167 |
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In contrast to storage ring BPMs with continuously sampling ADCs, BPMs of single-bunch linear accelerators with typical repetition rates of 10-100Hz may also use waveform digitisers that sample just during a short interval when the bunch is passing the pickup. At PSI a 12-channel analogue sampling chip called "DRS" has been developed (*) that samples input signals in an array of 1024 capacitors per channel at up to 5GSPS. The acquisition can be stopped by a trigger signal and then the capacitor voltages of all 12 channels can be digitised with a single commercial external ADC at 33MSPS, achieving ~11 bit effective DC resolution and 450MHz max. bandwidth. The DRS chip was originally developed for low-cost digitization of 3000 detector signals of a particle physics experiment, using the PSI "VPC" VME64x FPGA board as digital back-end equipped with two PMC mezzanine modules with two DRS chips each. However, such DRS-based systems are also an attractive solution for inexpensive direct sampling and FPGA-based post-processing of suitable BPM pickup signals. This paper discusses BPM-related properties, limitations, possible improvements and measurement results of DRS-based electronics.
*S. Ritt. The DRS chip: Cheap waveform digitizing in the GHz range, Nucl. Instrum. Meth. A518: 470-471, 2004. |