| |
The basic task of Libera Brilliance is electron beam position measurement. A secondary, but no less important, task is machine protection. Libera Brilliance activates Interlock output when the beam position is outside predefined limits. The Interlock subsystem also activates when the analog-to-digital converters (AD) are saturated and the beam position is only virtually centered. AD converter saturation is detected in the multiplexed fast peak detectors using AD converter rate data. The Interlock is designed for fail-safe operation. Within the FPGA window, a comparator function is performed on the Fast Acquisition position data delivered at a 10 kHz rate. Comparison is done separately for X and Y positions. Limits and operation mode are settable through the CSPI library. To avoid manual resetting of the Interlock, logic output is designed as a monostable cell. The described circuitry has been successfully implemented and tested in both laboratory and accelerator environments.
|
|