| Paper | Title | Page |
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| TUPC048 | Application of a 5 GSPS Analogue Ring Sampling Chip for Low-cost Single-shot BPM Systems | 1167 |
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In contrast to storage ring BPMs with continuously sampling ADCs, BPMs of single-bunch linear accelerators with typical repetition rates of 10-100Hz may also use waveform digitisers that sample just during a short interval when the bunch is passing the pickup. At PSI a 12-channel analogue sampling chip called "DRS" has been developed (*) that samples input signals in an array of 1024 capacitors per channel at up to 5GSPS. The acquisition can be stopped by a trigger signal and then the capacitor voltages of all 12 channels can be digitised with a single commercial external ADC at 33MSPS, achieving ~11 bit effective DC resolution and 450MHz max. bandwidth. The DRS chip was originally developed for low-cost digitization of 3000 detector signals of a particle physics experiment, using the PSI "VPC" VME64x FPGA board as digital back-end equipped with two PMC mezzanine modules with two DRS chips each. However, such DRS-based systems are also an attractive solution for inexpensive direct sampling and FPGA-based post-processing of suitable BPM pickup signals. This paper discusses BPM-related properties, limitations, possible improvements and measurement results of DRS-based electronics.
*S. Ritt. The DRS chip: Cheap waveform digitizing in the GHz range, Nucl. Instrum. Meth. A518: 470-471, 2004. |
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| THPC123 | The PSI DSP Carrier (PDC) Board - a Digital Back-end for Bunch-to-bunch and Global Orbit Feedbacks in Linear Accelerators and Storage Rings | 3272 |
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| PSI has developed a signal processing VXS/VME64x board for accelerator applications like low-latency bunch-to-bunch feedbacks, global orbit feedbacks or low-level RF systems. The board is a joint development of PSI/SLS staff and staff working on the contribution of PSI for the European X-ray FEL (E-XFEL). Future applications of the board include the Intra-Bunchtrain Feedback (IBFB) of the E-XFEL as well as the upgrade of the SLS Fast Orbit Feedback (FOFB) and Multibunch Feedback (MBFB). The PDC board has four Virtex-4 FPGAs, two TS201 Tiger Sharc DSPs, VXS and VME64x 2eSST interfaces, and two front panel SFP multi-gigabit fibre optic links. Two 500-pin LVDS/multi-gigabit mezzanine connectors allow to interface the FPGAs to two application-dependent mezzanine modules each containing e.g. four 500 Msps 12-bit ADCs and two 14-bit DACs for the IBFB and MBFB, or four multi-gigabit SFP fibre optic transceivers for the FOFB. This paper reports on hardware and firmware concepts, system topologies and synergies of future applications. |