| Paper | Title | Page |
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| TUPP003 | Automatic Generation of SEU Immunity for FPGA Based Electronics for Accelerators | 1529 |
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The modern accelerator control systems nowadays are build using digital technology based on FPGA circuits. However, digital circuits working in radioactive environment are exposed to disturbing effects, in particular SEU (Single Event Upset)*. One of the countermeasure is a redundancy in circuit that allow to detect and correct errors caused by radiation**. Unfortunately CAD software provides no support to automatically include required redundancy in the FPGA project. Moreover, optimization procedure removes all redundant parts and special effort must be made to prevent that. The paper presents a software environment to process VHDL description of the circuit and automatically generate the redundant blocks together with voting circuits. The generated redundancy uses Triple Module Redundancy (TMR) scheme. It also supports the VHDL simulation with SEUs in order to enable identification of the most sensitive components***. Since the TMR is costly, the designer can indicate which parts of the circuit should be replicated based on the results of simulation.
*Baumann. Neutron-induced…, Int. Rel. Phys. Symp. 2000. |