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Grecki, M. K.

Paper Title Page
MOPP129 Compensation of Lorentz Force Detuning for SC Linacs (with Piezo Tuners) 862
 
  • M. K. Grecki, J. Andryszczak, T. Pozniak, K. P. Przygoda, P. M.S. Sekalski
    TUL-DMCS, Łódź
 
  The superconducting linacs use niobium cavities working with extremely high quality factor. Therefore the bandwidth of the cavity is very narrow and even subtle deformation caused by Lorentz force detunes the cavity a lot. For high gradient operation (over 15MV/m) the mechanical deformation of the cavity should be compensated by piezo tuner*. The paper presents design of a piezo control system and the results of measurements of its efficiency. It was demonstrated in FLASH accelerator that an initial detuning of 300Hz can be compensated by single pulse excitation of the piezo. The described system consist of multichannel programmable pulse generator driving a 8 channel piezo amplifiers capable to supply piezos with pulses up to 1A and up to 80V. It can compensate for Lorentz force detuning in all three FLASH cryhomodules equipped with piezos (ACC3,5,6).

*Liepe et al. "Dynamic Lorentz Force Compensation with a Fast Piezoelectric Tuner," PAC2001, pp. 1074-1076.

 
TUPP003 Automatic Generation of SEU Immunity for FPGA Based Electronics for Accelerators 1529
 
  • M. K. Grecki, G. W. Jablonski, W. Jalmuzna, D. R. Makowski
    TUL-DMCS, Łódź
 
  The modern accelerator control systems nowadays are build using digital technology based on FPGA circuits. However, digital circuits working in radioactive environment are exposed to disturbing effects, in particular SEU (Single Event Upset)*. One of the countermeasure is a redundancy in circuit that allow to detect and correct errors caused by radiation**. Unfortunately CAD software provides no support to automatically include required redundancy in the FPGA project. Moreover, optimization procedure removes all redundant parts and special effort must be made to prevent that. The paper presents a software environment to process VHDL description of the circuit and automatically generate the redundant blocks together with voting circuits. The generated redundancy uses Triple Module Redundancy (TMR) scheme. It also supports the VHDL simulation with SEUs in order to enable identification of the most sensitive components***. Since the TMR is costly, the designer can indicate which parts of the circuit should be replicated based on the results of simulation.

*Baumann. Neutron-induced…, Int. Rel. Phys. Symp. 2000.
**Hentschke et al. Analyzing Area…, Symp. ICs and Systems Design, SBCCI02.
***Grecki. VHDL Simulation…, Nanotech 2006, Vol.1.