| Paper |
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Page |
| WPO004 |
News from the FAIR Control System under Development |
37 |
| WPI01 |
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- R. Bär, D.H. Beck, C. Betz, J. Fitzek, S. Jülicher, U. Krause, M. Thieme, R. Vincelli
GSI, Darmstadt, Germany
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The control system for the FAIR (Facility for Antiproton and Ion Research) accelerator facility is presently under development and implementation. The FAIR accelerators will extend the present GSI accelerator chain, then being used as injector, and provide anti-proton, ion, and rare isotope beams with unprecedented intensity and quality for a variety of research programs. This paper shortly summarizes the general status of the FAIR project and focusses on the progress of the control system design and its implementation. The poster presents the general system architecture and updates on the status of major building blocks of the control system. We highlight the control system implementation efforts for CRYRING, a new accelerator presently under recommissioning at GSI, which will serve as a test-ground for the complete control system stack and evaluation of the new controls concepts.
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Slides WPO004 [1.039 MB]
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| FPO017 |
Managing Multiple Function Generators for FAIR |
199 |
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- S. Rauch, R. Bär, M. Thieme
GSI, Darmstadt, Germany
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In the FAIR control system, equipment which needs to be controlled with ramped nominal values (e.g. power converters) is controlled by a standard front-end controller called scalable control unit (SCU). An SCU combines a ComExpressBoard with Intel CPU and an FPGA baseboard and acts as bus-master on the SCU host-bus. Up to 12 function generators can be implemented in slave-board FPGAs and can be controlled from one SCU. The real-time data supply for the generators demands a special software/hardware approach. Direct control of the generators with a FESA (front-end control software architecture) class, running on an Intel Atom CPU with Linux, does not meet the timing requirements. So an extra layer with an LM32 soft-core CPU is added to the FPGA. Communication between Linux and the LM32 is done via shared memory and a circular buffer data structure. The LM32 supplies the function generators with new parameter sets when it is triggered by interrupts. This two-step approach decouples the Linux CPU from the hard real-time requirements. For synchronous start and coherent clocking of all function generators, special pins on the SCU backplane are being used to avoid bus latencies.
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Poster FPO017 [1.098 MB]
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