PCaPAC2014 - List of Authors (Rauch, S.)

Paper

Title

Page

Launching the FAIR Timing System with CRYRING

155

M. Kreider
Glyndŵr University, Wrexham, United Kingdom
R. Bär, D.H. Beck, A. Hahn, M. Kreider, C. Prados, S. Rauch, W.W. Terpstra, M. Zweig
GSI, Darmstadt, Germany
J.N. Bai
IAP, Frankfurt am Main, Germany

During the past two years, significant progress has been made on the development of the General Machine Timing system for the upcoming FAIR facility at GSI. The prime features are time-synchronization of 2000-3000 nodes using the White Rabbit Precision-Time-Protocol (WR-PTP), distribution of International Atomic Time (TAI) time stamps and synchronized command and control of FAIR control system equipment. A White Rabbit network has been set up connecting parts of the existing facility and a next version of the Timing Master has been developed. Timing Receiver nodes in form factors Scalable Control Unit (standard front-end controller for FAIR), VME, PCIe and standalone have been developed. CRYRING is the first machine on the GSI/FAIR campus to be operated with this new timing system and serves as a test-ground for the complete control system. Installation of equipment starts in late spring followed by commissioning of equipment in summer 2014.

Slides TCO304 [7.818 MB]

FPO017

Managing Multiple Function Generators for FAIR

199

S. Rauch, R. Bär, M. Thieme
GSI, Darmstadt, Germany

In the FAIR control system, equipment which needs to be controlled with ramped nominal values (e.g. power converters) is controlled by a standard front-end controller called scalable control unit (SCU). An SCU combines a ComExpressBoard with Intel CPU and an FPGA baseboard and acts as bus-master on the SCU host-bus. Up to 12 function generators can be implemented in slave-board FPGAs and can be controlled from one SCU. The real-time data supply for the generators demands a special software/hardware approach. Direct control of the generators with a FESA (front-end control software architecture) class, running on an Intel Atom CPU with Linux, does not meet the timing requirements. So an extra layer with an LM32 soft-core CPU is added to the FPGA. Communication between Linux and the LM32 is done via shared memory and a circular buffer data structure. The LM32 supplies the function generators with new parameter sets when it is triggered by interrupts. This two-step approach decouples the Linux CPU from the hard real-time requirements. For synchronous start and coherent clocking of all function generators, special pins on the SCU backplane are being used to avoid bus latencies.

Poster FPO017 [1.098 MB]

FPO024

First Idea on Bunch to Bucket Transfer for FAIR

210

J.N. Bai
IAP, Frankfurt am Main, Germany
R. Bär, D.H. Beck, T. Ferrand, M. Kreider, D. Ondreka, C. Prados, S. Rauch, W.W. Terpstra, M. Zweig
GSI, Darmstadt, Germany

The FAIR facility makes use of the General Machine Timing (GMT) system and the Bunch phase Timing System (BuTiS) to realize the synchronization of two machines. In order to realize the bunch to bucket transfer, firstly, the source machine slightly detunes its RF frequency at its RF flattop. Secondly, the source and target machines exchange packets over the timing network shortly before the transfer and make use of the RF frequency-beat method to realize the synchronization between both machines with accuracy better than 1o. The data of the packet includes RF frequency, timestamp of the zero-crossing point of the RF signal, harmonic number and bunch/bucket position. Finally, both machines have all information of each other and can calculate the coarse window and create announce signals for triggering kickers.

Poster FPO024 [2.077 MB]

Paper	Title	Page
TCO304	Launching the FAIR Timing System with CRYRING	155
	M. Kreider Glyndŵr University, Wrexham, United Kingdom R. Bär, D.H. Beck, A. Hahn, M. Kreider, C. Prados, S. Rauch, W.W. Terpstra, M. Zweig GSI, Darmstadt, Germany J.N. Bai IAP, Frankfurt am Main, Germany
	During the past two years, significant progress has been made on the development of the General Machine Timing system for the upcoming FAIR facility at GSI. The prime features are time-synchronization of 2000-3000 nodes using the White Rabbit Precision-Time-Protocol (WR-PTP), distribution of International Atomic Time (TAI) time stamps and synchronized command and control of FAIR control system equipment. A White Rabbit network has been set up connecting parts of the existing facility and a next version of the Timing Master has been developed. Timing Receiver nodes in form factors Scalable Control Unit (standard front-end controller for FAIR), VME, PCIe and standalone have been developed. CRYRING is the first machine on the GSI/FAIR campus to be operated with this new timing system and serves as a test-ground for the complete control system. Installation of equipment starts in late spring followed by commissioning of equipment in summer 2014.
	Slides TCO304 [7.818 MB]

FPO017	Managing Multiple Function Generators for FAIR	199
	S. Rauch, R. Bär, M. Thieme GSI, Darmstadt, Germany
	In the FAIR control system, equipment which needs to be controlled with ramped nominal values (e.g. power converters) is controlled by a standard front-end controller called scalable control unit (SCU). An SCU combines a ComExpressBoard with Intel CPU and an FPGA baseboard and acts as bus-master on the SCU host-bus. Up to 12 function generators can be implemented in slave-board FPGAs and can be controlled from one SCU. The real-time data supply for the generators demands a special software/hardware approach. Direct control of the generators with a FESA (front-end control software architecture) class, running on an Intel Atom CPU with Linux, does not meet the timing requirements. So an extra layer with an LM32 soft-core CPU is added to the FPGA. Communication between Linux and the LM32 is done via shared memory and a circular buffer data structure. The LM32 supplies the function generators with new parameter sets when it is triggered by interrupts. This two-step approach decouples the Linux CPU from the hard real-time requirements. For synchronous start and coherent clocking of all function generators, special pins on the SCU backplane are being used to avoid bus latencies.
	Poster FPO017 [1.098 MB]

FPO024	First Idea on Bunch to Bucket Transfer for FAIR	210
	J.N. Bai IAP, Frankfurt am Main, Germany R. Bär, D.H. Beck, T. Ferrand, M. Kreider, D. Ondreka, C. Prados, S. Rauch, W.W. Terpstra, M. Zweig GSI, Darmstadt, Germany
	The FAIR facility makes use of the General Machine Timing (GMT) system and the Bunch phase Timing System (BuTiS) to realize the synchronization of two machines. In order to realize the bunch to bucket transfer, firstly, the source machine slightly detunes its RF frequency at its RF flattop. Secondly, the source and target machines exchange packets over the timing network shortly before the transfer and make use of the RF frequency-beat method to realize the synchronization between both machines with accuracy better than 1o. The data of the packet includes RF frequency, timestamp of the zero-crossing point of the RF signal, harmonic number and bunch/bucket position. Finally, both machines have all information of each other and can calculate the coarse window and create announce signals for triggering kickers.
	Poster FPO024 [2.077 MB]