PCaPAC2014 - List of Authors (Nishiyama, K.)

Paper	Title	Page
FPO019	FPGA Utilization in the Accelerator Interlock System (About the MPS Development in the LIPAc)	204
	K. Nishiyama Japan Atomic Energy Agency (JAEA), International Fusion Energy Research Center (IFERC), Rokkasho, Kamikita, Aomori, Japan R. Gobin CEA/IRFU, Gif-sur-Yvette, France J. Knaster, A. Marqueta Barbero, Y. Okumura IFMIF/EVEDA, Rokkasho, Japan T. Kojima, T. Narita, H. Sakaki, H. Takahashi JAEA, Aomori, Japan
	The development of IFMIF (International Fusion Material Irradiation Facility) to generate a 14 MeV source of neutrons with the spectrum of DT fusion reactions is indispensable to qualify suitable materials for the First Wall of the nuclear vessel in fusion power plants. As part of IFMIF validation activities , LIPAc (Linear IFMIF Prototype Accelerator) facility, currently under installation at Rokkasho (Japan) , will accelerate a 125mA CW and 9MeV deuteron beam with a total beam power of 1.125MW. The Machine Protection System (MPS) of LIPAc provides an essential interlock function of stopping the beam in case of anomalous beam loss or other hazardous situations. High speed processing is necessary to achieve properly the MPS main goal. This high speed processing of the signals, distributed alongside the accelerator facility, is based on FPGA technology. This paper describes the basis of FPGA use in the accelerator interlock system through the development of LIPAc’s MPS, with a comparison with using of FPGA of the other accelerator control system.

Paper

Title

Page

FPGA Utilization in the Accelerator Interlock System (About the MPS Development in the LIPAc)

204

K. Nishiyama
Japan Atomic Energy Agency (JAEA), International Fusion Energy Research Center (IFERC), Rokkasho, Kamikita, Aomori, Japan
R. Gobin
CEA/IRFU, Gif-sur-Yvette, France
J. Knaster, A. Marqueta Barbero, Y. Okumura
IFMIF/EVEDA, Rokkasho, Japan
T. Kojima, T. Narita, H. Sakaki, H. Takahashi
JAEA, Aomori, Japan

The development of IFMIF (International Fusion Material Irradiation Facility) to generate a 14 MeV source of neutrons with the spectrum of DT fusion reactions is indispensable to qualify suitable materials for the First Wall of the nuclear vessel in fusion power plants. As part of IFMIF validation activities , LIPAc (Linear IFMIF Prototype Accelerator) facility, currently under installation at Rokkasho (Japan) , will accelerate a 125mA CW and 9MeV deuteron beam with a total beam power of 1.125MW. The Machine Protection System (MPS) of LIPAc provides an essential interlock function of stopping the beam in case of anomalous beam loss or other hazardous situations. High speed processing is necessary to achieve properly the MPS main goal. This high speed processing of the signals, distributed alongside the accelerator facility, is based on FPGA technology. This paper describes the basis of FPGA use in the accelerator interlock system through the development of LIPAc’s MPS, with a comparison with using of FPGA of the other accelerator control system.