Paper |
Title |
Page |
FPO022 |
New developments on the FAIR Data Master |
207 |
FPI03 |
|
|
- M. Kreider, J. Davies, V. Grout
Glyndŵr University, Wrexham, United Kingdom
- R. Bär, D.H. Beck, M. Kreider, W.W. Terpstra
GSI, Darmstadt, Germany
|
|
|
During the last year, a small scale timing system has been built with a first version of the Data Master. In this paper, we will describe field test progress as well as new design concepts and implementation details of the new prototype to be tested with the CRYRING accelerator timing system. The message management layer has been introduced as a hardware acceleration module for the timely dispatch of control messages. It consists of a priority queue for outgoing messages, combined with a scheduler and network load balancing. This loosens the real-time constraints for the CPUs composing the control messages noticeably, making the control firmware very easy to construct and deterministic. It is further opening perspectives away from the current virtual machine-like implementation on to a specialized programming language for accelerator control. In addition, a streamlined and better fitting model for beam production chains and cycles has been devised for use in the data master firmware. The processing worst case execution time becomes completely calculable, enabling fixed time-slices for safe multiplexing of cycles in all of the CPUs.
|
|
|
Slides FPO022 [0.890 MB]
|
|
|