Author: Baer, R.     [Bär, R.]
Paper Title Page
WPO004 News from the FAIR Control System under Development 37
WPI01   use link to see paper's listing under its alternate paper code  
 
  • R. Bär, D.H. Beck, C. Betz, J. Fitzek, S. Jülicher, U. Krause, M. Thieme, R. Vincelli
    GSI, Darmstadt, Germany
  
  The control system for the FAIR (Facility for Antiproton and Ion Research) accelerator facility is presently under development and implementation. The FAIR accelerators will extend the present GSI accelerator chain, then being used as injector, and provide anti-proton, ion, and rare isotope beams with unprecedented intensity and quality for a variety of research programs. This paper shortly summarizes the general status of the FAIR project and focusses on the progress of the control system design and its implementation. The poster presents the general system architecture and updates on the status of major building blocks of the control system. We highlight the control system implementation efforts for CRYRING, a new accelerator presently under recommissioning at GSI, which will serve as a test-ground for the complete control system stack and evaluation of the new controls concepts.  
slides icon Slides WPO004 [1.039 MB]  
 
TCO201 Managing the FAIR Control System Development 135
 
  • R. Bär, F. Ameil
    GSI, Darmstadt, Germany
  
  After years of careful preparation and planning, construction and implementation works for the new international accelerator complex FAIR (Facility for Antiproton and Ion Research) at GSI have seriously been started. The FAIR accelerators will extend the present GSI accelerator chain, then being used as injector, and provide anti-proton, ion, and rare isotope beams with unprecedented intensity and quality for a variety of research programs. The accelerator control system for the FAIR complex is presently being designed and developed by the GSI Controls group with a team of about 50 soft- and hardware developers, complemented by an international in-kind contribution from the FAIR member state Slovenia. This paper presents requirements and constraints from being a large and international project and focusses on the organizational and project management strategies and tools for the control system subproject. This includes the project communication, design methodology, release cycle planning, testing strategies and ensuring technical integrity and coherence of the whole system during the full project phase.  
slides icon Slides TCO201 [2.781 MB]  
 
TCO304 Launching the FAIR Timing System with CRYRING 155
 
  • M. Kreider
    Glyndŵr University, Wrexham, United Kingdom
  • R. Bär, D.H. Beck, A. Hahn, M. Kreider, C. Prados, S. Rauch, W.W. Terpstra, M. Zweig
    GSI, Darmstadt, Germany
  • J.N. Bai
    IAP, Frankfurt am Main, Germany
  
  During the past two years, significant progress has been made on the development of the General Machine Timing system for the upcoming FAIR facility at GSI. The prime features are time-synchronization of 2000-3000 nodes using the White Rabbit Precision-Time-Protocol (WR-PTP), distribution of International Atomic Time (TAI) time stamps and synchronized command and control of FAIR control system equipment. A White Rabbit network has been set up connecting parts of the existing facility and a next version of the Timing Master has been developed. Timing Receiver nodes in form factors Scalable Control Unit (standard front-end controller for FAIR), VME, PCIe and standalone have been developed. CRYRING is the first machine on the GSI/FAIR campus to be operated with this new timing system and serves as a test-ground for the complete control system. Installation of equipment starts in late spring followed by commissioning of equipment in summer 2014.  
slides icon Slides TCO304 [7.818 MB]  
 
FPO017 Managing Multiple Function Generators for FAIR 199
 
  • S. Rauch, R. Bär, M. Thieme
    GSI, Darmstadt, Germany
  
  In the FAIR control system, equipment which needs to be controlled with ramped nominal values (e.g. power converters) is controlled by a standard front-end controller called scalable control unit (SCU). An SCU combines a ComExpressBoard with Intel CPU and an FPGA baseboard and acts as bus-master on the SCU host-bus. Up to 12 function generators can be implemented in slave-board FPGAs and can be controlled from one SCU. The real-time data supply for the generators demands a special software/hardware approach. Direct control of the generators with a FESA (front-end control software architecture) class, running on an Intel Atom CPU with Linux, does not meet the timing requirements. So an extra layer with an LM32 soft-core CPU is added to the FPGA. Communication between Linux and the LM32 is done via shared memory and a circular buffer data structure. The LM32 supplies the function generators with new parameter sets when it is triggered by interrupts. This two-step approach decouples the Linux CPU from the hard real-time requirements. For synchronous start and coherent clocking of all function generators, special pins on the SCU backplane are being used to avoid bus latencies.  
poster icon Poster FPO017 [1.098 MB]  
 
FPO022 New developments on the FAIR Data Master 207
FPI03   use link to see paper's listing under its alternate paper code  
 
  • M. Kreider, J. Davies, V. Grout
    Glyndŵr University, Wrexham, United Kingdom
  • R. Bär, D.H. Beck, M. Kreider, W.W. Terpstra
    GSI, Darmstadt, Germany
  
  During the last year, a small scale timing system has been built with a first version of the Data Master. In this paper, we will describe field test progress as well as new design concepts and implementation details of the new prototype to be tested with the CRYRING accelerator timing system. The message management layer has been introduced as a hardware acceleration module for the timely dispatch of control messages. It consists of a priority queue for outgoing messages, combined with a scheduler and network load balancing. This loosens the real-time constraints for the CPUs composing the control messages noticeably, making the control firmware very easy to construct and deterministic. It is further opening perspectives away from the current virtual machine-like implementation on to a specialized programming language for accelerator control. In addition, a streamlined and better fitting model for beam production chains and cycles has been devised for use in the data master firmware. The processing worst case execution time becomes completely calculable, enabling fixed time-slices for safe multiplexing of cycles in all of the CPUs.  
slides icon Slides FPO022 [0.890 MB]  
 
FPO024 First Idea on Bunch to Bucket Transfer for FAIR 210
 
  • J.N. Bai
    IAP, Frankfurt am Main, Germany
  • R. Bär, D.H. Beck, T. Ferrand, M. Kreider, D. Ondreka, C. Prados, S. Rauch, W.W. Terpstra, M. Zweig
    GSI, Darmstadt, Germany
  
  The FAIR facility makes use of the General Machine Timing (GMT) system and the Bunch phase Timing System (BuTiS) to realize the synchronization of two machines. In order to realize the bunch to bucket transfer, firstly, the source machine slightly detunes its RF frequency at its RF flattop. Secondly, the source and target machines exchange packets over the timing network shortly before the transfer and make use of the RF frequency-beat method to realize the synchronization between both machines with accuracy better than 1o. The data of the packet includes RF frequency, timestamp of the zero-crossing point of the RF signal, harmonic number and bunch/bucket position. Finally, both machines have all information of each other and can calculate the coarse window and create announce signals for triggering kickers.  
poster icon Poster FPO024 [2.077 MB]