PAC2013 - List of Authors (Klaus, A.)

Paper	Title	Page
THPMA01	Fast FPGA Based Low-Trigger-Jitter Waveform Generator Method for Barrier-Bucket Electronics at FAIR	1352
	E. Bayer, P. Zipf University of Kassel, Kassel, Germany A. Klaus, H. Klingbeil, G. Schreiber GSI, Darmstadt, Germany
	A new method for low trigger-jitter waveform generation is presented. The targeted application is the time-delayed, trigger synchronous waveform generation. The method can be implemented on a single FPGA, which drives an ADC. The phase-jitter between a trigger signal fed to the FPGA and the generated single sine waveform is less than 90 ps RMS and 275 ps peak-to-peak. The response time of the wave form generator is 50 ns. The waveform generator was designed for the use in the “Barrier-Bucket” system of the SIS100 synchrotron at the new Facility for Antiproton and Ion Research (FAIR) in Darmstadt, Germany. The BB-system will be deployed in the pre-compression stage after the acceleration process to compress the accelerated particles to 1/3 of the synchrotron circumference. This will be done by generating two moving single sine waves synchronously to the revolution trigger of the synchrotron. To compress the beam with a minimal longitudinal emittance blow-up the phase-shifting has to be performed adiabatically. For SIS100 this means that the moving step size should be less than 1 ns. The amplitude and the offset of each sine wave can also be manipulated in real time.

Paper

Title

Page

Fast FPGA Based Low-Trigger-Jitter Waveform Generator Method for Barrier-Bucket Electronics at FAIR

1352

E. Bayer, P. Zipf
University of Kassel, Kassel, Germany
A. Klaus, H. Klingbeil, G. Schreiber
GSI, Darmstadt, Germany

A new method for low trigger-jitter waveform generation is presented. The targeted application is the time-delayed, trigger synchronous waveform generation. The method can be implemented on a single FPGA, which drives an ADC. The phase-jitter between a trigger signal fed to the FPGA and the generated single sine waveform is less than 90 ps RMS and 275 ps peak-to-peak. The response time of the wave form generator is 50 ns. The waveform generator was designed for the use in the “Barrier-Bucket” system of the SIS100 synchrotron at the new Facility for Antiproton and Ion Research (FAIR) in Darmstadt, Germany. The BB-system will be deployed in the pre-compression stage after the acceleration process to compress the accelerated particles to 1/3 of the synchrotron circumference. This will be done by generating two moving single sine waves synchronously to the revolution trigger of the synchrotron. To compress the beam with a minimal longitudinal emittance blow-up the phase-shifting has to be performed adiabatically. For SIS100 this means that the moving step size should be less than 1 ns. The amplitude and the offset of each sine wave can also be manipulated in real time.