Author: Gilpatrick, J.D.
Paper Title Page
THPAC25 LANSCE-RM Wire Scanners: SLIP-Encoded Serial Communication for Maintenance Display at the Instrument 1196
 
  • J.D. Sedillo, J.D. Gilpatrick
    LANL, Los Alamos, New Mexico, USA
 
  Funding: U.S. Department of Energy
The newest LANSCE-RM wire scanner control systems at Los Alamos National Laboratory’s LANSCE particle accelerator facility utilize touch-panel displays for limited status and control at the instrument. Since the wire scanner control hardware utilizes a National Instruments CompactRIO embedded controller, no display may be interfaced to the CompactRIO via conventional means. Thus, in order to display information from the CompactRIO, a touch-panel display and computer combo unit has been added to each wire scanner control chassis with information being exchanged via a common, RS-232 interface. This paper describes the maintenance features available at the touch screen and the underlying SLIP communication scheme used for simple packetized transfer of data between the touch-panel display and the CompactRIO.
 
 
THPAC26 Analog Front End Design for High Speed Digitizing of Beam Position and Phase Measurements at LANSCE 1199
 
  • H.A. Watkins, J.D. Gilpatrick, R.C. McCrady
    LANL, Los Alamos, New Mexico, USA
 
  Funding: Work supported by the U.S. Department of Energy.
The Los Alamos Neutron Science Center (LANSCE) is currently developing beam position and phase measurements for its 805-MHz linac as part of the LANSCE risk mitigation project. Beam position and phase monitors (BPPMs) with four shorted striplines have been installed throughout the linac. The BPPM electronics will sample each stripline at 240 MS/s and use a field programmable gate array (FPGA) to calculate position and phase of the beam relative to the linac reference. The beam micro-pulses from each electrode must be filtered and amplified to provide the correct frequency and amplitude level to the digitizer. This paper describes the signal conditioning required to interface LANSCE BPPMs to high speed digitizers, the diagnostic capabilities of the analog front end (AFE) module, digital control of the AFE module and design considerations to meet these objectives.