IPAC2015 - List of Authors (Bai, J.N.)

Paper	Title	Page
WEPMA024	System Design for a Deterministic Bunch-to-Bucket Transfer	2809
	T. Ferrand TEMF, TU Darmstadt, Darmstadt, Germany J.N. Bai IAP, Frankfurt am Main, Germany
	Funding: Supported by GSI and the Technical University Darmstadt in the frame of the cooperation for FAIR. A deterministic bunch to bucket transfer system is currently under development in the frame of the FAIR project at GSI. To achieve our accuracy and stability requirements, a set of hardware modules will be implemented. These hardware modules are expected to provide values such as the relative phase advance between the RF systems of both, the source and the target synchrotron according to an external timing system. These values are exchanged via optical fibers between different supply rooms, and the considered RF signals are re-synthesized locally. These re-synthesized signals are synchronized to enable a precise phase advance control between the synchrotrons’ RF systems. The first step of the development consists in modeling the actual DDS and DSP-based LLRF environment of the SIS18 under Ptolemy-II. Measurements on real devices will be performed concurrently to the simulation. We expect to use this simulation to refine our timing expectations regarding the synchronization process and the inter-module communication protocols and design the synchronization function, which will be implemented on the hardware modules.
DOI •	reference for this paper ※ https://doi.org/10.18429/JACoW-IPAC2015-WEPMA024
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Paper

Title

Page

System Design for a Deterministic Bunch-to-Bucket Transfer

2809

T. Ferrand
TEMF, TU Darmstadt, Darmstadt, Germany
J.N. Bai
IAP, Frankfurt am Main, Germany

Funding: Supported by GSI and the Technical University Darmstadt in the frame of the cooperation for FAIR.
A deterministic bunch to bucket transfer system is currently under development in the frame of the FAIR project at GSI. To achieve our accuracy and stability requirements, a set of hardware modules will be implemented. These hardware modules are expected to provide values such as the relative phase advance between the RF systems of both, the source and the target synchrotron according to an external timing system. These values are exchanged via optical fibers between different supply rooms, and the considered RF signals are re-synthesized locally. These re-synthesized signals are synchronized to enable a precise phase advance control between the synchrotrons’ RF systems. The first step of the development consists in modeling the actual DDS and DSP-based LLRF environment of the SIS18 under Ptolemy-II. Measurements on real devices will be performed concurrently to the simulation. We expect to use this simulation to refine our timing expectations regarding the synchronization process and the inter-module communication protocols and design the synchronization function, which will be implemented on the hardware modules.

DOI •

reference for this paper ※ https://doi.org/10.18429/JACoW-IPAC2015-WEPMA024

Export •

reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)