IPAC2013 - List of Authors (Zhao, L.Y.)

Paper	Title	Page
WEPME032	Development Status of SINAP Timing System	2992
	M. Liu, D.K. Liu, C.X. Yin, L.Y. Zhao SINAP, Shanghai, People's Republic of China
	After successful implementation of SINAP timing solution at Pohang Light Source in 2011, the development of SINAP timing system version-II was finished by the end of 2012. The hardware of version-II is based on Virtex-6 FPGA chip, and bidirectional event frame transfer is realized in a 2.5Gbps fiber network. In event frame, data transfer functionality substitutes for distributed bus. The structure of timing system is also modified, where a new versatile EVO could be configured as EVG, FANOUT and EVR with optical outputs. Besides standard VME modules, we designed PLC-EVR as well, which is compatible with Yokogawa F3RP61 series. Based on brand new hardware architecture, the jitter performance of SINAP timing system version-II is improved remarkably.

WEPME033	Status of SSRF Fast Orbit Feedback System	2995
	C.X. Yin, B.C. Jiang, L.Y. Zhao SINAP, Shanghai, People's Republic of China
	As a 3rd generation light source, Shanghai Synchrotron Radiation Facility (SSRF) is pushing the requirement of beam stability to sub-micron in the range of DC to 100Hz. A fast orbit feedback system was designed and implemented to satisfy this requirement. In this paper, the layout of SSRF fast orbit feedback system, the structure of its electronics system and its hardware and software subsystems are described. The current status of SSRF fast orbit feedback system is presented.

Paper

Title

Page

Development Status of SINAP Timing System

2992

M. Liu, D.K. Liu, C.X. Yin, L.Y. Zhao
SINAP, Shanghai, People's Republic of China

After successful implementation of SINAP timing solution at Pohang Light Source in 2011, the development of SINAP timing system version-II was finished by the end of 2012. The hardware of version-II is based on Virtex-6 FPGA chip, and bidirectional event frame transfer is realized in a 2.5Gbps fiber network. In event frame, data transfer functionality substitutes for distributed bus. The structure of timing system is also modified, where a new versatile EVO could be configured as EVG, FANOUT and EVR with optical outputs. Besides standard VME modules, we designed PLC-EVR as well, which is compatible with Yokogawa F3RP61 series. Based on brand new hardware architecture, the jitter performance of SINAP timing system version-II is improved remarkably.

WEPME033

Status of SSRF Fast Orbit Feedback System

2995

C.X. Yin, B.C. Jiang, L.Y. Zhao
SINAP, Shanghai, People's Republic of China

As a 3rd generation light source, Shanghai Synchrotron Radiation Facility (SSRF) is pushing the requirement of beam stability to sub-micron in the range of DC to 100Hz. A fast orbit feedback system was designed and implemented to satisfy this requirement. In this paper, the layout of SSRF fast orbit feedback system, the structure of its electronics system and its hardware and software subsystems are described. The current status of SSRF fast orbit feedback system is presented.