Author: Liu, D.K.
Paper Title Page
WEPME032 Development Status of SINAP Timing System 2992
  • M. Liu, D.K. Liu, C.X. Yin, L.Y. Zhao
    SINAP, Shanghai, People's Republic of China
  After successful implementation of SINAP timing solution at Pohang Light Source in 2011, the development of SINAP timing system version-II was finished by the end of 2012. The hardware of version-II is based on Virtex-6 FPGA chip, and bidirectional event frame transfer is realized in a 2.5Gbps fiber network. In event frame, data transfer functionality substitutes for distributed bus. The structure of timing system is also modified, where a new versatile EVO could be configured as EVG, FANOUT and EVR with optical outputs. Besides standard VME modules, we designed PLC-EVR as well, which is compatible with Yokogawa F3RP61 series. Based on brand new hardware architecture, the jitter performance of SINAP timing system version-II is improved remarkably.