Author: Chai, J.-S.
Paper Title Page
WEPME036 The Development of LLRF System at PAL 3004
  • K.-H. Park, H.S. Han, Y.-G. Jung, D.E. Kim, H.-G. Lee, H.S. Suh
    PAL, Pohang, Kyungbuk, Republic of Korea
  • J.-S. Chai, Y.S. Lee
    SKKU, Suwon, Republic of Korea
  • B.-K. Kang
    POSTECH, Pohang, Kyungbuk, Republic of Korea
  The PAL has been developing the low level radio frequency (LLRF) system. The required field stabilities of the LLRF system are within ±0.75% in amplitude and 0.35° in phase in a cavity. All the hardware including RF front–end, FPGA with peripherals such as ADC, DAC, Oscillator and digital interface were assembled. The sub-modules for the RF signal processing were written by VHDL and integrated to test at the local facility. The macroblaze software processor was implemented to make the system simple in interfacing to peripherals and to secure flexibility later. This paper described the microblaze processor which was ported into the VERTEX6 FPGA. And also this paper showed the test results of the each module and integrated into the full system.